EP0341897A2
Expired / Lapsed
EP
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Content addressable memory array architecture
Assignee: Advanced Micro Devices Inc
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Filing: 1989-05-04
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Granted: —
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Expires: 2009-05-04
Abstract
Abstract A content addressable memory system includes a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells, a plurality of word lines extending through the array for addressing different words in the memory cells, each of the words comprising a plurality of adjacent cells extending in a first direction in the array, a plurality of match lines extending through the array in parallel with the word lines in the first direction, a plurality of bit lines extending through the array in a second direction perpendicular to the first direction, each of the bit lines communicating with the cells in one of the columns extending in the second direction, and a pair of registers connected to the bit lines for performing masking operations on bits in the array.
Inventors
- 👤 Patrick T. Chuang
- 👤 Robert L. Yau
- 👤 Hiroshi Yoshida
- 👤 Moon-Yee Wang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 06:15
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04; G06; G06F; G06F16/00; G06F16/90; G06F16/903; G06F16/90335; G06F16/90339
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
151 words
A content addressable memory system comprising: a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells; a plurality of word lines extending through said array for addressing different words in said memory cells, each of said words comprising a plurality of adjacent ones of said cells extending in a first direction in said array; a plurality of match lines extending through said array in parallel with said word lines in said first direction; and a plurality of bit lines extending through said array in a second direction perpendicular to said first direction, each of said bit lines communicating with said cells in one column of said cells extending through said array in said second direction; said bit lines being configured in pairs, with a pair of said bit lines communicating with each of said cells in each of said columns.
Claim 2
Dependent Claim
151 words
A content addressable memory system comprising: a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells; a plurality of word lines extending through said array for addressing different words in said memory cells, each of said words comprising a plurality of adjacent ones of said cells extending in a first direction in said array; a plurality of match lines extending through said array in parallel with said word lines in said first direction; and a plurality of bit lines extending through said array in a second direction perpendicular to said first direction, each of said bit lines communicating with said cells in one column of said cells extending through said array in said second direction; said bit lines being configured in pairs, with a pair of said bit lines communicating with each of said cells in each of said columns.
Claim 3
Dependent Claim
114 words
A system in accordance with claim 1 including: an I/O bus; bit line descriptor circuiting associated with each of said pairs of bit lines; said bit line descriptor circuitry including: a comparand register, a mask register, a sense amplifier, a programmable bit line writing circuit; means for supplying data to be written into said cells from said data bus to said comparand register; means for supplying said data to be written from said comparand register to said programmable bit line writing circuit; and means for supplying said data to be written from said programmable bit line writing circuit to all of said pairs of said bit lines in a given one of said columns.
Claim 4
Dependent Claim
46 words
A system in accordance with Claim 2 including: means for connecting one of said sense amplifiers to said pair of bit lines of its associated column to read data from one of said cells in said column which is enabled by one of said word lines.
Claim 5
Dependent Claim
84 words
A system in accordance with Claim 2 including: means for performing a match operation on data stored in said cells, said match performing means including means for disabling said word select lines; means for supplying selected match data to said programmable bit lines from said comparand register and said mask register; means for simultaneously comparing said selected match data with the data in said cells; and means for detecting the occurrence of matches between said selected match data and said data in said cells.
Claim 6
Dependent Claim
110 words
A system in accordance with Claim 2 including means for performing a masking operation on data to be stored in said cells, said mask performing means including, means for supplying to said mask register selected signal bits corresponding to data bits to be masked in said cells; means for supplying data bits to be stored in said cells; means for comparing said supplied data bits with the contents of said mask register to eliminate from said supplied data bits those bits which correspond to said selected signal bits corresponding to said data bits to be masked; and means for communicating said supplied bits remaining after said comparing to said cells.
Claim 7
Dependent Claim
25 words
A system in accordance with Claim 5 in which said supplied bits to be stored are transmitted from an I/O bus to said comparand register.
Claim 8
Dependent Claim
32 words
A system in accordance with Claim 6 in which said selected signal bits corresponding to data to be masked in said cells are transmitted from said comparand register to said mask register.
Claim 9
Dependent Claim
56 words
A system in accordance with Claim 7 in which said selected signal bits corresponding to data to be masked in said cells is first transmitted from said I/O bus to said comparand register and then to said mask register, and said supplied bits to be stored are transmitted from said I/O bus to said comparand register.
Claim 10
Dependent Claim
32 words
A system in accordance with Claim 5 in which said comparand register and said mask register have a bit capacity which is a multiple of the bit capacity of said I/O bus.
References Cited (Backward Citations)
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