High density multi-level metallization and interconnection structure

Claim 1

A multi-level semiconductor device, comprising: a substrate; a plurality of insulating layers forming levels on the substrate; an upper conductive wiring pattern on an upper level and a lower conductive wiring pattern on a lower level and on a first insulating layer having an upper surface, the lower conductive wiring pattern having sidewalls extending in a substantially vertical direction from the upper surface of the first insulating layer; and at least one conductive via comprising a through-hole filled with metal electrically connecting the upper conductive wiring pattern to the lower conductive wiring pattern, the conductive via comprising a bottom surface and extending through a second insulating layer to the lower conductive wiring pattern in direct contact with the second insulating layer; wherein the bottom surface of the conductive via is in direct contact with the lower conductive wiring pattern and with an etch stop insulating material different from the second insulating layer, and the etch stop insulating material extends from the upper surface of the first insulating layer in contact with the substantially vertical side surfaces of the lower conductive wiring pattern.