US5236870A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a semiconductor integrated circuit utilizing insulators which react distinctly from each other
Assignee: Fujifilm Business Innovation Corp
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Filing: 1991-11-26
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Granted: 1993-08-17
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Expires: 2011-11-26
Abstract
Abstract A semiconductor integrated circuit providing a novel patterned multilayered wiring structure to enhance the degree of the integration of the circuit and the speed of the operation. The structure includes at least one first interlaid electric insulator film on the wall of the contact portion of a first wiring layer and its vicinity, a second interlaid electric insulator film, which reacts distinctly to the etching process utilized from the first interlaid electric insulator film, is provided on a substrate.
Inventors
- 👤 Yasushi Sakata
- 👤 Toshimichi Iwamori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:36
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
228 words
A method of making a semiconductor integrated circuit having a substrate, comprising the steps of: forming a first conductive wiring layer on said substrte via sputtering; photopatterning said formed first wiring layer to generate a circuit pattern; forming a first interlaid electric insulator film over said photopatterned first wiring layer via plasma chemical vapor deposition; anisotropic dry-etching said formed first interlaid insulator film with a first gas including CF 4 and H 2 to remove a portion of said first interlaid electric insulator film and expose at least a portion of said photopatterned first wiring layer; forming a second interlaid electric insulator film over said dry-etched first interlaid insulator film and said exposed portion of said photopatterned first wiring layer via pressure-reduction chemical vapor deposition; photopatterning said second interlaid electric insulator film to form a contact hole therein by reactive ion-etching said second interlaid electric insulator film with a second gas including CF 4 and H 2 to remove a portion of said second interlaid electric insulator film and re-exposed said exposed portion of said photopatterned first wiring layer, said second gas having a higher ratio of CF 4 to H 2 than that in said first gas; and forming a second conductive wiring layer over said photopatterned second interlaid insulator film via sputtering to form a contact with said re-exposed portion of said photopatterned first wiring layer.
Claim 2
Independent Claim
228 words
A method of making a semiconductor integrated circuit having a substrate, comprising the steps of: forming a first conductive wiring layer on said substrte via sputtering; photopatterning said formed first wiring layer to generate a circuit pattern; forming a first interlaid electric insulator film over said photopatterned first wiring layer via plasma chemical vapor deposition; anisotropic dry-etching said formed first interlaid insulator film with a first gas including CF 4 and H 2 to remove a portion of said first interlaid electric insulator film and expose at least a portion of said photopatterned first wiring layer; forming a second interlaid electric insulator film over said dry-etched first interlaid insulator film and said exposed portion of said photopatterned first wiring layer via pressure-reduction chemical vapor deposition; photopatterning said second interlaid electric insulator film to form a contact hole therein by reactive ion-etching said second interlaid electric insulator film with a second gas including CF 4 and H 2 to remove a portion of said second interlaid electric insulator film and re-exposed said exposed portion of said photopatterned first wiring layer, said second gas having a higher ratio of CF 4 to H 2 than that in said first gas; and forming a second conductive wiring layer over said photopatterned second interlaid insulator film via sputtering to form a contact with said re-exposed portion of said photopatterned first wiring layer.
Claim 3
Dependent Claim
46 words
A method of making a semiconductor integrated circuit according to claim 1, further comprising the step of rotatively applying or centrifugally casting a spin-on-glass film over said formed first interlaid insulator film and subsequently baking said glass film, before forming said second interlaid insulator film thereover.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-16 | 1997-02-15 | 1997-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-16 | 2001-02-15 | 2001-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-16 | 2005-02-15 | 2005-08-17 | $7700.00 | Window Closed / Lapsed |