US5014109A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Miniaturization of a contact hole in a semiconductor device
Assignee: Toshiba Corp
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Filing: 1989-08-01
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Granted: 1991-05-07
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Expires: 2009-08-01
Abstract
Abstract The present invention provides a semiconductor device, comprising a substrate, a first insulation layer formed on the substrate, a first wiring layer formed on the first insulation layer, a second insulation layer formed on the first wiring layer and having a contact hole, and a third insulation layer formed on the second insulation layer, said third insulation layer being in contact with the first wiring layer via the contact hole.
Inventors
- 👤 Takayoshi Higuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:06
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10W20/056; H10W20/071; H10W20/081
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
165 words
A semiconductor structure providing for connection between wiring layers, comprising: a semiconductor substrate; a first insulating layer formed on said substrate; a first wiring layer formed on said first insulating layer; a second insulating layer formed on said first wiring layer and having a contact hole, said contact hole being provided with a hole portion formed directly under a bottom of said contact hole, said hole portion passing through said first insulating layer and said first wiring layer and reaching said substrate; means filling said hole portion of said contact hole for preventing said first wiring layer from contacting said semiconductor substrate; and a second wiring layer filling said contact hole and formed on said second insulating layer and said means filling said hole portion, and connected to said first wiring layer; wherein said contact hole serves solely to connect said first wiring layer to said second wiring layer and said means filling said hole portion of said contact hole prevents short-circuiting of the device.
Claim 2
Dependent Claim
165 words
A semiconductor structure providing for connection between wiring layers, comprising: a semiconductor substrate; a first insulating layer formed on said substrate; a first wiring layer formed on said first insulating layer; a second insulating layer formed on said first wiring layer and having a contact hole, said contact hole being provided with a hole portion formed directly under a bottom of said contact hole, said hole portion passing through said first insulating layer and said first wiring layer and reaching said substrate; means filling said hole portion of said contact hole for preventing said first wiring layer from contacting said semiconductor substrate; and a second wiring layer filling said contact hole and formed on said second insulating layer and said means filling said hole portion, and connected to said first wiring layer; wherein said contact hole serves solely to connect said first wiring layer to said second wiring layer and said means filling said hole portion of said contact hole prevents short-circuiting of the device.
Claim 3
Dependent Claim
25 words
The semiconductor device according to claim 1, further comprising a second wiring layer buried in the contact hole in contact with the first wiring layer.
Claim 4
Dependent Claim
22 words
The semiconductor device according to claim 1, further comprising a field oxide layer interposed between the substrate and the second insulating layer.
Claim 5
Dependent Claim
13 words
The semiconductor device according to claim 1, wherein the substrate is of P-type.
Claim 6
Dependent Claim
23 words
The semiconductor device according to claim 1, further comprising a source region, a drain region and a gate region formed on the substrate.
Claim 7
Dependent Claim
24 words
The semiconductor device according to claim 1, wherein the first wiring layer acts as a gate electrode positioned between source region and drain. regions.
Claim 8
Dependent Claim
21 words
The semiconductor device according to claim 1, wherein the first wiring layer is formed by anisotropic etching using a resist pattern.
Claim 9
Dependent Claim
20 words
The semiconductor device according to claim 1, wherein the contact hole is formed by anisotropic etching using a resist pattern.
Claim 10
Dependent Claim
22 words
The semiconductor device according to claim 1, wherein the third insulating layer is a silicon nitride layer formed by low pressure CVD.
Claim 11
Dependent Claim
38 words
The semiconductor device according to claim 1, wherein the third insulating layer has a thickness not less than half the width of said hole portion of said contact hole constituting a groove formed in the second insulating layer.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-06 | 1994-11-05 | 1995-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-06 | 1998-11-05 | 1999-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-06 | 2002-11-05 | 2003-05-07 | $7700.00 | Window Closed / Lapsed |