Static random-access memory having multilevel conductive layer

Claim 2

A semiconductor memory having static cells each composed of two driver MOS transistors formed on a semiconductor substrate and two transfer MOS transistors and two load resistors, which are formed on said substrate and are connected to the drains of said driver MOS transistors, respectively, said memory further comprising a capacitance element formed on said substrate, said capacitance element having two electrodes being electrically connected in said memory so as to supply a charge stored in said capacitance element to a storage node of said memory, said memory also including a conductive film for fixing the sources of said driver MOS transistors to a ground voltage, said conductive film being formed above said semiconductor substrate, said conductive film defining one electrode of said capacitance element formed on said substrate, said memory further comprising a conductive film for supplying a power supply voltage to said memory, said conductive film for supplying a power supply voltage being electrically coupled to the load resistors, the other of the two electrodes of the capacitance element being electrically connected to the load resistors.

Claim 3

A semiconductor memory according to claim 1, wherein said conductive film is formed over said load resistors formed on said semiconductor substrate so as t constitute an electric field shield for said load resistors.

Claim 4

A semiconductor memory according to claim 1, further comprising a conductive film for supplying a power supply voltage to said memory, wherein said conductive film for fixing the sources of said driver MOS transistors to a ground voltage is formed in the same layer as said conductive film for supplying a power supply voltage to said memory.

Claim 5

A semiconductor memory according to claim 1, further comprising data lines, and a conductive film electrically connecting the drains of said transfer MOS transistors and said data lines, and wherein said conductive film for fixing the source of said driver MOS transistors to a ground voltage is formed in the same layer as said conductive film electrically connecting the drains of said transfer MOS transistors and said data lines.

Claim 6

A semiconductor memory according to claim 1, further comprising data lines, a conductive film for supplying a power supply voltage to said memory, and a conductive film electrically connecting the drains of said transfer MOS transistors and said data lines, and wherein said conductive film for fixing the sources of said driver MOS transistors to a ground voltage, said conductive film for supplying a power supply voltage to said memory, and said conductive film electrically connecting the drains of said transfer MOS transistors and said data lines, are formed in the same conductive layer.

Claim 7

A semiconductor memory according to claim 1, wherein gate electrodes of the driver MOS transistors are formed from a first-level conductive layer on the substrate, the two load resistors are formed from a second-level conductive layer over the first-level conductive layer, and said conductive film is formed from a third-level conductive layer, also over the first-level conductive layer.

Claim 8

A semiconductor memory according to claim 6, wherein said third-level conductive layer is formed over the second-level conductive layer, whereby the conductive film is formed from a conductive layer over the load resistors.

Claim 9

A semiconductor memory according to claim 7, further comprising data lines, and a further conductive film electrically connecting the drains of said transfer MOS transistors and said data lines, said further conductive film being formed of one of said second-level conductive layer and said third-level conductive layer.

Claim 10

A semiconductor memory according to claim 8, wherein said further conductive film is formed of said third-level conductive layer.

Claim 11

A semiconductor memory according to claim 9, further comprising insulating films surrounding the gate electrodes of the transfer MOS transistors, a further insulating film between the gate electrodes of the transfer MOS transistors and the second-level conductive layer, and a still further insulating film between the second-level conductive layer and the third-level conductive layer, the sum of the thicknesses of said further insulating film and still further insulating film being smaller than the thickness of the insulating films surrounding the gate electrodes of the transfer MOS transistors.

Claim 12

A semiconductor memory according to claim 10, wherein the insulating films surrounding the gate electrodes of the transfer MOS transistors include first insulating films on the gate electrodes and second insulating films at the side of the gate electrodes.

Claim 13

A semiconductor memory according to claim 10, wherein the further conductive film directly electrically connects to the drains of said transfer MOS transistors and directly electrically connects to the data lines, and wherein the electrical connection between the data line and further conductive film is over the gate electrode of a transfer MOS transistor.

Claim 14

A semiconductor memory according to claim 10, wherein said data line and said further conductive film are in direct electrical connection, the electrical connection being over the gate electrode of a transfer MOS transistor.

Claim 15

A semiconductor memory according to claim 6, wherein said second-level conductive layer is formed over the third-level conductive layer, whereby the load resistors are formed from a conductive layer over said conductive film.

Claim 16

A semiconductor memory according to claim 14, including a further conductive film, formed of said second-level conductive layer, and adapted to supply a power supply voltage to the memory.

Claim 17

A semiconductor memory according to claim 15, wherein the further conductive film is electrically connected to a still further conductive film, formed from the third-level conductive layer, so as to supply a power supply voltage to the memory.

Claim 18

A semiconductor memory comprising: first and second driver MOS transistors, first and second transfer MOS transistors, and first and second load resistors; the gate electrode of said first driver MOS transistor, one terminal of said second load resistor, one of the source and drain of said second transfer MOS transistor and one of the drain source of said second driver MOS transistor being electrically connected together; the gate electrode of said second driver MOS transistor, one terminal of said first load resistor, one of the source and drain of said first transfer MOS transistor and one of the drain and source of said first driver MOS transistor being electrically connected together; the other terminals of said first and second load resistors being connected to a first predetermined power supply line; the gate electrodes of said first and second transfer MOS transistors being mutually defined by a first-level conductive layer including polycrystalline silicon, said gate electrodes acting as a word line; one of the sources and drains of each of said first and second driver MOS transistors being mutually connected to a second predetermined power supply line; one of the drains and sources of each of said first and second transfer MOS transistors being connected to first and second data lines, respectively; said first and second load resistors being defined by a second-level conductive layer including polycrystalline silicon; said first or second predetermined power supply line being defined by a third-level conductive layer including polycrystalline silicon; and said second- and third-level conductive layers including polycrystalline silicon forming in combination a capacitance element, said capacitance element being electrically connected in said memory so as to supply a charge stored in said capacitance element to a storage node of said memory.

Claim 19

A semiconductor memory comprising: first and second driver MOS transistors, first and second transfer MOS transistors, and first and second load resistors; the gate electrode of said first driver MOS transistor, one terminal of said second load resistor, one of the source and drain of said second transfer MOS transistor and one of the drain source of said second driver MOS transistor being electrically connected together; the gate electrode of said second driver MOS transistor, one terminal of said first load resistor, one of the source and drain of said first transfer MOS transistor and one of the drain and source of said first driver MOS transistor being electrically connected together; the other terminals of said first and second load resistors being connected to a first predetermined power supply line; the gate electrodes of said first and second transfer MOS transistors being mutually defined by a first-level conductive layer including polycrystalline silicon, said gate electrodes acting as a word line; one of the sources and drains of each of said first and second driver MOS transistors being mutually connected to a second predetermined power supply line; one of the drains and sources of each of said first and second transfer MOS transistors being connected to first and second data lines, respectively; said first and second load resistors being defined by a second-level conductive layer including polycrystalline silicon; said first or second predetermined power supply line being defined by a third-level conductive layer including polycrystalline silicon; and said second- and third-level conductive layers including polycrystalline silicon forming in combination a capacitance element, said capacitance element being electrically connected in said memory so as to supply a charge stored in said capacitance element to a storage node of said memory.

Claim 20

A semiconductor memory comprising: first and second driver MOS transistors, first and second transfer MOS transistors, and first and second load resistors; the gate electrode of said first driver MOS transistor, one terminal of said second load resistor, one of the source and drain of said second transfer MOS transistor and one of the drain and source of said second driver MOS transistor being electrically connected together; the gate electrode of said second driver MOS transistor, one terminal of said first load resistor, one of the source and drain of said first transfer MOS transistor and one of the drain and source of said first driver MOS transistor being electrically connected together; the other terminals of said first and second load resistors being connected to a first predetermined power supply line; the gate electrodes of sad first and second transfer MOS transistors being mutually defined by a first-level conductive layer including polycrystalline silicon, said gate electrode acting as a word line; one of the sources and drains of each of said first and second driver MOS transistors being mutually connected to a second predetermined power supply line; one of the drains and sources of each of said first and second transfer MOS transistors being connected to first and second data lines, respectively; said first and second load resistors and said second predetermined power supply line being defined by a second-level conductive layer including polycrystalline silicon; said first predetermined power supply line being defined by a third-level conductive layer including polycrystalline silicon; and said second- and third-level conductive layers including polycrystalline silicon forming in combination a capacitance element, said capacitance element being electrically connected in said memory so as to supply a charge stored in said capacitance element to a storage node of said memory.

Claim 21

A semiconductor memory comprising: first and second driver MOS transistors, first and second transfer MOS transistors, and first and second load resistors; the gate electrode of said first driver MOS transistor, one terminal of said second load resistor, one of the source and drain of said second transfer MOS transistor and one of the drain and source of said second driver MOS transistor being electrically connected together; the gate electrode of said second driver MOS transistor, one terminal of said first load resistor, one of the source and drain of said first transfer MOS transistor and one of the drain and source of said first driver MOS transistor being electrically connected together; the other terminals of said first and second load resistors being connected to a first predetermined power supply line; the gate electrodes of sad first and second transfer MOS transistors being mutually defined by a first-level conductive layer including polycrystalline silicon, said gate electrode acting as a word line; one of the sources and drains of each of said first and second driver MOS transistors being mutually connected to a second predetermined power supply line; one of the drains and sources of each of said first and second transfer MOS transistors being connected to first and second data lines, respectively; said first and second load resistors and said second predetermined power supply line being defined by a second-level conductive layer including polycrystalline silicon; said first predetermined power supply line being defined by a third-level conductive layer including polycrystalline silicon; and said second- and third-level conductive layers including polycrystalline silicon forming in combination a capacitance element, said capacitance element being electrically connected in said memory so as to supply a charge stored in said capacitance element to a storage node of said memory.

Claim 22

A semiconductor memory comprising: first and second driver MOS transistors, first and second transfer MOS transistors, and first and second load resistors; the gate electrode of said first driver MOS transistor, one terminal of said second load resistor, one of the source and drain of said second transfer MOS transistor, and one of the drain and source of said second driver MOS transistor being electrically connected together; the gate electrode of said second driver MOS transistor, one terminal of said first load resistor, one of the source and drain of said first transfer MOS transistor, and one of the drain and source of said first driver MOS transistor being electrically connected together; the other terminals of said first and second load resistors being connected to a first predetermined power supply line; the gate electrodes of said first and second transfer MOS transistors being mutually defined by a first-level conductive layer including polycrystalline silicon, said gate electrodes acting as a word line; one of the sources and drains of each of said first and second driver MOS transistors being mutually connected to a second predetermined power supply line; one of the drains and sources of each of said first and second transfer MOS transistors being connected to first and second data lines, respectively; said first and second load resistors being defined by a third-level conductive layer including polycrystalline silicon; said first or second predetermined power supply line being defined by a second-level conductive layer including polycrystalline silicon; and said second- and third-level conductive layers including polycrystalline silicon forming in combination a capacitance element, said capacitance element being electrically connected in said memory so as to supply a charge stored in said capacitance element to a storage node of said memory.

Claim 23

A semiconductor memory comprising: first and second driver MOS transistors, first and second transfer MOS transistors, and first and second load resistors; the gate electrode of said first driver MOS transistor, one terminal of said second load resistor, one of the source and drain of said second transfer MOS transistor, and one of the drain and source of said second driver MOS transistor being electrically connected together; the gate electrode of said second driver MOS transistor, one terminal of said first load resistor, one of the source and drain of said first transfer MOS transistor, and one of the drain and source of said first driver MOS transistor being electrically connected together; the other terminals of said first and second load resistors being connected to a first predetermined power supply line; the gate electrodes of said first and second transfer MOS transistors being mutually defined by a first-level conductive layer including polycrystalline silicon, said gate electrodes acting as a word line; one of the sources and drains of each of said first and second driver MOS transistors being mutually connected to a second predetermined power supply line; one of the drains and sources of each of said first and second transfer MOS transistors being connected to first and second data lines, respectively; said first and second load resistors being defined by a third-level conductive layer including polycrystalline silicon; said first or second predetermined power supply line being defined by a second-level conductive layer including polycrystalline silicon; and said second- and third-level conductive layers including polycrystalline silicon forming in combination a capacitance element, said capacitance element being electrically connected in said memory so as to supply a charge stored in said capacitance element to a storage node of said memory.

Claim 24

A semiconductor memory according to claim 1, wherein the capacitance element is formed over said load resistors.

Claim 25

A semiconductor memory according to claim 20, wherein said conductive film defining one electrode of said capacitance element defines the upper electrode of said capacitance element.

Claim 26

A semiconductor memory according to claim 21, wherein the load resistors are formed from a second-level conductive layer over the substrate, with the lower electrode of said capacitance element also being formed from said second-level conductive layer.

Claim 27

A semiconductor memory according to claim 1, wherein said conductive film defining one electrode of said capacitance element defines the upper electrode of said capacitance element.

Claim 28

A semiconductor memory according to claim 23, wherein the load resistors are formed from a second-level conductive layer over the substrate, with the lower electrode of said capacitance element aids being formed from said second-level conductive layer.