Semiconductor element layout method employing process migration

Claim 2

A semiconductor element layout method comprising the steps of: selectively removing substrate contacts from a first mask layout prepared for integrated circuits according to a first design rule which requires at least a first minimum spacing between the substrate contacts; and carrying out process migration to convert the first mask layout, from which some of said substrate contacts have been removed, into a second mask layout that follows a second design rule which requires at least a second minimum spacing that is smaller than the first minimum spacing of the first design rule.

Claim 3

The method as claimed in claim 1, further comprising the step of selectively removing substrate contacts that are present between adjacent elements.

Claim 4

The method as claimed in claim 2, wherein the process migration step carries substrate contacts that are present in a space between dissimilar wells on the first mask layout into the second mask layout, and removes substrate contacts that are present in the wells on the first mask layout.

Claim 5

The method as claimed in claim 2, wherein the process migration step removes substrate contacts that are on or attached to a power supply trunk on the first mask layout.

Claim 6

The method as claimed in claim 2, wherein the process migration step removes substrate contacts that are adjacent to each other on the first mask layout.

Claim 7

The method as claimed in claim 2, wherein the process migration step keeps substrate contacts that are indirectly connected to a power supply trunk through a layer that is different from the power supply trunk, and removes substrate contacts that are directly connected to the power supply trunk.

Claim 8

The method as claimed in claim 2, wherein the process migration step converts substrate contacts on the first mask layout into Joint contacts on the second mask layout.

Claim 9

The method as claimed in claim 2, wherein the process migration step converts substrate contacts on the first mask layout into butting contacts on the second mask layout.

Claim 10

The method as claimed in claim 2, wherein the process migration step converts substrate contacts on the first mask layout into borderless contacts on the second mask layout.

Claim 11

The method as claimed in claim 2, wherein the process migration step divides a substrate contact on the first mask layout into square contacts of uniform size.

Claim 12

The method as claimed in claim 2, wherein the process migration step removes substrate contacts from a power supply line on the first mask layout and converts the power supply line into a path of uniform thickness on the second mask layout.

Claim 13

The method as claimed in claim 2, wherein the process migration step grows contacts, substrate diffusion layers, and layers to be short-circuited to them, obtains an OR region of these grown contacts and layers, obtains an ANDNOT region of the OR region and wells, removes a power source from a metal conductive layer, inverts the power-source-removed metal conductive layer, scales down the inverted region by a predetermined value, finds an AND region of the ANDNOT region and the scaled-down inverted region, and forms substrate contacts in the AND region.

Claim 14

The method as claimed in claim 1, further comprising the step of preparing a symbolic layout according to the the first mask layout with the selectively removed substrate contacts, and forming substrate contacts on the symbolic layout.

Claim 15

The method as claimed in claim 1, wherein the second mask layout is a symbolic layout.

Claim 16

A semiconductor element layout method comprising the steps of: selectively removing substrate contacts from a first mask layout prepared for integrated circuits according to a first design rule which requires at least a first minimum width for each of the substrate contacts; and carrying out process migration to convert the first mask layout, from which some of said substrate contacts have been removed, into a second mask layout that follows a second design rule which requires at least a second minimum width for the substrate contacts that is less that the first minimum width of the first design rule.

Claim 17

A semiconductor element layout method comprising the steps of: selectively removing substrate contacts from a first mask layout prepared for integrated circuits according to a first design rule which requires at least a first minimum width for each of the substrate contacts; and carrying out process migration to convert the first mask layout, from which some of said substrate contacts have been removed, into a second mask layout that follows a second design rule which requires at least a second minimum width for the substrate contacts that is less that the first minimum width of the first design rule.

Claim 18

The method as claimed in claim 15, further comprising the step of selectively removing the substrate contacts that are present between adjacent elements.

Claim 19

The method as claimed in claim 16, wherein the process migration step carries substrate contacts that are present in a space between dissimilar wells on the first mask layout into the second mask layout, and removes substrate contacts that are present in the wells on the first mask layout.

Claim 20

The method as claimed in claim 16, wherein the process migration step keeps substrate contacts that are indirectly connected to a power supply trunk through a layer that is different from the power supply trunk, and removes substrate contracts that are directly connected to the power supply trunk.

Claim 21

The method as claimed in claim 16, wherein the process migration step converts substrate contacts on the first mask layout into joint contacts on the second mask layout.

Claim 22

The method as claimed in claim 16, wherein the process migration step converts substrate contacts on the first mask layout into butting contacts on the second mask layout.