US5018074A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making gate array masks
Assignee: RTX Corp
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Filing: 1988-11-04
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Granted: 1991-05-21
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Expires: 2008-11-04
Abstract
Abstract A method for making gate array masks in which a mask set for an existing set of gate array cells are converted to follow new design rules requiring a non-uniform transformation of circuit components is carried out by manually converting a defining set of circuit components from a first set of grid points to a second set, the second set being specified by the new design rules, and thereafter automatically converting grid points in the remaining gate array cells to the new system.
Inventors
- 👤 J. Stephen Griffith
- 👤 Patricia L. Roberts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:42
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
381 words
A method of making a derivative set of masks for a set of integrated circuit gate array logic cells based on a column structure of gates, from a first set of masks containing a set of mask elements having predetermined characteristic dimensions and predetermined associated grid points, following a first set of design rules, comprising the steps of: specifying grid points and corresponding dimensions, in a first coordinate system, of a defining set of mask elements of said set of integrated circuit gate array logic cells, including said column structure, in accordance with said first set of design rules, whereby a digital representation of said defining set of mask elements is established that includes at least one grid point in said first grid system for each member of said defining set, said dimensions and location of all components of said defining set in said first coordinate system being stored in predetermined association with said at least one grid point; specifying corresponding reference points of all components in all cells of said set of integrated circuit gate array logic cells in terms of said first grid system, thereby establishing a first digital representation of said set of logic cells in which each component of said set of logic cells is represented by a reference grid position in said first grid system; storing said first digital representation of said symbolic representation in a storage medium; altering dimensions and grid positions in said coordinate system of said mask elements of said defining set in accordance with said second set of design rules, thereby defining a second grid system ranging over said defining set, whereby a nonlinear coordinate transformation is established between grid points of said defining set in said first grid system and corresponding grid points in said second grid system, and; in an automatic data processing system, stepping through said first digital representation of at least one other cell in said set of logic cells and transforming grid points of at least one component of said at least one other cell according to said defined transformation, whereby said at least one component of said at least one other logic cell is characterized by a second digital representation related to said second grid system and in accordance with said second set of design rules.
Claim 2
Independent Claim
381 words
A method of making a derivative set of masks for a set of integrated circuit gate array logic cells based on a column structure of gates, from a first set of masks containing a set of mask elements having predetermined characteristic dimensions and predetermined associated grid points, following a first set of design rules, comprising the steps of: specifying grid points and corresponding dimensions, in a first coordinate system, of a defining set of mask elements of said set of integrated circuit gate array logic cells, including said column structure, in accordance with said first set of design rules, whereby a digital representation of said defining set of mask elements is established that includes at least one grid point in said first grid system for each member of said defining set, said dimensions and location of all components of said defining set in said first coordinate system being stored in predetermined association with said at least one grid point; specifying corresponding reference points of all components in all cells of said set of integrated circuit gate array logic cells in terms of said first grid system, thereby establishing a first digital representation of said set of logic cells in which each component of said set of logic cells is represented by a reference grid position in said first grid system; storing said first digital representation of said symbolic representation in a storage medium; altering dimensions and grid positions in said coordinate system of said mask elements of said defining set in accordance with said second set of design rules, thereby defining a second grid system ranging over said defining set, whereby a nonlinear coordinate transformation is established between grid points of said defining set in said first grid system and corresponding grid points in said second grid system, and; in an automatic data processing system, stepping through said first digital representation of at least one other cell in said set of logic cells and transforming grid points of at least one component of said at least one other cell according to said defined transformation, whereby said at least one component of said at least one other logic cell is characterized by a second digital representation related to said second grid system and in accordance with said second set of design rules.
Claim 3
Dependent Claim
52 words
A method according to claim 1, further including the step of plotting, under stored program control, a predetermined mask cell subset of mask elements for each of at least one logic cell of said set of logic cells, thereby forming a representation of one mask of a set of integrated circuit masks.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-20 | 2002-11-19 | 2003-05-21 | $7700.00 | Window Closed / Lapsed |