US5477467A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Shrinkable BiCMOS circuit layout
Assignee: NXP USA Inc
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Filing: 1992-06-01
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Granted: 1995-12-19
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Expires: 2012-06-01
Abstract
Abstract A BiCMOS integrated circuit design having an oversized isolation area surrounding circuit elements which are non-scaleable is provided. The non-scaleable circuit elements can be removed from the layout, and the remaining scaleable elements shrunk by a CAD system. After shrinking the scaleable elements and the isolation area, the non-scaleable elements are returned to the layout at their original size, and located within the scaled-down isolation area.
Inventors
- 👤 James M. Rugg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 00:34
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398; H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D89/00; H10D89/10
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
63 words
An integrated circuit comprising: an isolation region; a first circuit type outside of the isolation region; a second circuit type inside the isolation region, wherein excess space is left between the periphery of the second circuit type and the boundary of the isolation region so that the first circuit type and the isolation region can be downsized without shrinking the second circuit type.
Claim 2
Dependent Claim
63 words
An integrated circuit comprising: an isolation region; a first circuit type outside of the isolation region; a second circuit type inside the isolation region, wherein excess space is left between the periphery of the second circuit type and the boundary of the isolation region so that the first circuit type and the isolation region can be downsized without shrinking the second circuit type.
Claim 3
Dependent Claim
32 words
The integrated circuit of claim 1 wherein the first circuit type comprises bipolar circuitry and the second circuit type comprises CMOS circuitry, and the oversized excess space uniformly surrounds the isolation region.
Claim 4
Independent Claim
119 words
A method of generating a digital record using a computer aided design (CAD) system providing the basis for a photomask of a scaleable integrated circuit having CMOS circuit elements and bipolar circuit elements, each of the bipolar circuit elements being surrounded by an isolation area, wherein a P% size reduction is anticipated for the CMOS circuit elements and the isolation areas have a minimum isolation width W min , the method comprising the steps of: identifying scaleable and non-scaleable circuit elements; drawing the non-scaleable elements using a CAD system; drawing an isolation region using the CAD system having a width ##EQU3## around the non-scaleable elements; and drawing the scaleable elements using the CAD system outside of the isolation region.
Claim 5
Independent Claim
119 words
A method of generating a digital record using a computer aided design (CAD) system providing the basis for a photomask of a scaleable integrated circuit having CMOS circuit elements and bipolar circuit elements, each of the bipolar circuit elements being surrounded by an isolation area, wherein a P% size reduction is anticipated for the CMOS circuit elements and the isolation areas have a minimum isolation width W min , the method comprising the steps of: identifying scaleable and non-scaleable circuit elements; drawing the non-scaleable elements using a CAD system; drawing an isolation region using the CAD system having a width ##EQU3## around the non-scaleable elements; and drawing the scaleable elements using the CAD system outside of the isolation region.
Claim 6
Dependent Claim
92 words
The method of claim 3 further comprising the step of: removing a first portion of the digital record corresponding to the non-scaleable elements from the digital record; processing the remaining portion of the digital record using a program in the CAD system to arithmetically shrink the remaining portion of the digital record corresponding to the scaleable elements including the isolation region; and placing first portion of the digital record corresponding to the the non-scaleable elements into the processed portion of the digital record corresponding to a location inside of the isolation region.
Claim 7
Independent Claim
184 words
A method of laying out an integrated circuit having a first and a second type of circuitry using at least in part a programmed computer aided design (CAD) system, the method comprising: generating a first generation digital record using a CAD system a first generation photomask wherein a first portion of the first generation mask corresponds to a first circuitry type, a second portion of the first generation digital record corresponds to an electrically inactive buffer zone surrounding the first circuitry type, and a third portion of the first generation digital record corresponds to a second circuitry type placed outside of the buffer zone; and generating a second generation digital record using the CAD system thereby providing the basis of a second generation photomask by processing the second and third portions of the first generation digital record corresponding to the buffer zone using a program on the CAD system to arithmetically shrink the buffer zone and the second circuitry type of the first generation digital record while not processing the first portion of the first generation digital record corresponding to the first circuitry type.
Claim 8
Independent Claim
184 words
A method of laying out an integrated circuit having a first and a second type of circuitry using at least in part a programmed computer aided design (CAD) system, the method comprising: generating a first generation digital record using a CAD system a first generation photomask wherein a first portion of the first generation mask corresponds to a first circuitry type, a second portion of the first generation digital record corresponds to an electrically inactive buffer zone surrounding the first circuitry type, and a third portion of the first generation digital record corresponds to a second circuitry type placed outside of the buffer zone; and generating a second generation digital record using the CAD system thereby providing the basis of a second generation photomask by processing the second and third portions of the first generation digital record corresponding to the buffer zone using a program on the CAD system to arithmetically shrink the buffer zone and the second circuitry type of the first generation digital record while not processing the first portion of the first generation digital record corresponding to the first circuitry type.
Claim 9
Dependent Claim
21 words
The method of claim 5 wherein the first circuitry type comprises bipolar transistors and the second circuitry type comprises CMOS transistors.
Claim 10
Independent Claim
142 words
A method of laying out an integrated circuit having a first and a second type of circuitry using at least in part a programmed computer aided design (CAD) system, the method comprising: generating a first generation digital record that provides a basis of a first generation photomask, wherein generating the first generation mask further comprises: laying out a first circuitry type using a CAD system; laying out a first buffer zone using the CAD system, wherein the first buffer zone is of a first width, is void of circuitry, and uniformly surrounds the first circuitry type; laying out a second circuitry type outside of the buffer zone using the CAD system; and laying out a second buffer zone of a second width using the CAD system wherein the Second buffer zone is void of circuitry and uniformly surrounds the second circuitry type.
Claim 11
Independent Claim
142 words
A method of laying out an integrated circuit having a first and a second type of circuitry using at least in part a programmed computer aided design (CAD) system, the method comprising: generating a first generation digital record that provides a basis of a first generation photomask, wherein generating the first generation mask further comprises: laying out a first circuitry type using a CAD system; laying out a first buffer zone using the CAD system, wherein the first buffer zone is of a first width, is void of circuitry, and uniformly surrounds the first circuitry type; laying out a second circuitry type outside of the buffer zone using the CAD system; and laying out a second buffer zone of a second width using the CAD system wherein the Second buffer zone is void of circuitry and uniformly surrounds the second circuitry type.
Claim 12
Dependent Claim
106 words
The method of claim 16 further comprising the step of: generating a first intermediate digital record by removing data corresponding to the first circuitry type from the first generation digital record; generating a second intermediate digital record by down scaling the second circuitry type and the first and second buffer zones by processing a remaining portion of the first generation digital record with a program in the CAD system; and generating a second generation digital record by replacing the data corresponding to the first circuitry type into the second intermediate digital records, wherein the second generation digital record provides a basis for a second generation photomask.
Claim 13
Dependent Claim
52 words
The method of claim 8 wherein the first buffer zone width of the second generation photomask is W min , the second circuitry type and the first and second buffer zones are down scaled by P%, and the buffer zone width of the first generation photomask is at least W min /1-P%.
Claim 14
Dependent Claim
20 words
The method of claim 7 wherein the first buffer zone is an isolation region surrounding the first type of circuitry.
Claim 15
Dependent Claim
19 words
The method of claim 10 wherein the first circuitry type is bipolar and the second circuitry type is CMOS.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-18 | 1999-06-19 | 1999-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-18 | 2003-06-19 | 2003-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-18 | 2007-06-19 | 2007-12-19 | $7700.00 | Window Closed / Lapsed |