US5019534A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process of making self-aligned contact using differential oxidation
Assignee: Promos Technologies Inc
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Filing: 1989-10-31
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Granted: 1991-05-28
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Expires: 2009-10-31
Abstract
Abstract A process of forming a self-aligned oxide layer covering conductive structures such as MOS transistor gates above a semiconductive substrate while portions of the substrate such as source/drain regions are exposed involves forming side wall spacers against the gates, applying refractory metal to the exposed surface, heating the refractory metal so that it forms refractory silicide at regions where the refractory metal contacts the substrate, removing the unreacted refractory metal, and oxidizing the exposed refractory silicide with a low temperature wet oxidation which causes faster oxide growth above the highly doped gates than above the lightly doped source/drain regions. Subsequent etching of the differentially grown oxide layer exposes the source/drain regions while leaving protected the gate regions. Since no mask was needed for forming and patterning the gate-covering oxide, no misalignment can occur and thus no space need be allowed in the circuit layout for misalignment. In one embodiment, spacing between adjacent MOS transistor gates is reduced from 2.4 microns to 1.2 microns.
Inventors
- 👤 Nan-Hsiung Tsai
- 👤 Yun-Sheng Hwang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:56
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; Y; Y10; Y10S; Y10S148/00; Y10S148/019; Y10S438/00; Y10S438/911; Y10S438/981
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
237 words
A method for forming an integrated circuit structure comprising the steps of: forming above a silicon substrate conductive structures of polysilicon, said conductive structures having top surfaces and sidewalls, said polysilicon being sufficiently more heavily doped than said silicon substrate that a subsequent step of oxidizing a refractory silicide to be formed on said silicon substrate and said polysilicon conductive structures is sufficiently faster above said polysilicon conductive structures than above said silicon substrate that uniform oxide removal can expose said silicide above said silicon substrate and not expose said silicide above said polysilicon conductive structures; forming sidewall spacers against said sidewalls, said sidewall spacers being formed from an electrically insulating material; forming a layer of refractory metal on a top surface of said integrated circuit structure, said refractory metal contacting said top surfaces of said conductive structures, said side wall spacers, and exposed portions of said silicon substrate; heating said integrated circuit structure sufficiently to cause portions of said refractory metal which contact said top surfaces of said conductive structures and said exposed portions of said silicon substrate to form said refractory silicide; removing unreacted portions of said refractory metal; oxidizing said refractory silicide; and removing oxide using a process which occurs at a constant rate for all exposed oxide, said removing continuing to an extent which exposes said refractory silicide contacting said silicon substrate and does not expose said refractory silicide contacting said conductive structures.
Claim 2
Independent Claim
237 words
A method for forming an integrated circuit structure comprising the steps of: forming above a silicon substrate conductive structures of polysilicon, said conductive structures having top surfaces and sidewalls, said polysilicon being sufficiently more heavily doped than said silicon substrate that a subsequent step of oxidizing a refractory silicide to be formed on said silicon substrate and said polysilicon conductive structures is sufficiently faster above said polysilicon conductive structures than above said silicon substrate that uniform oxide removal can expose said silicide above said silicon substrate and not expose said silicide above said polysilicon conductive structures; forming sidewall spacers against said sidewalls, said sidewall spacers being formed from an electrically insulating material; forming a layer of refractory metal on a top surface of said integrated circuit structure, said refractory metal contacting said top surfaces of said conductive structures, said side wall spacers, and exposed portions of said silicon substrate; heating said integrated circuit structure sufficiently to cause portions of said refractory metal which contact said top surfaces of said conductive structures and said exposed portions of said silicon substrate to form said refractory silicide; removing unreacted portions of said refractory metal; oxidizing said refractory silicide; and removing oxide using a process which occurs at a constant rate for all exposed oxide, said removing continuing to an extent which exposes said refractory silicide contacting said silicon substrate and does not expose said refractory silicide contacting said conductive structures.
Claim 3
Dependent Claim
14 words
Method as in claim 1 in which said silicon substrate is lightly doped silicon.
Claim 4
Dependent Claim
27 words
Method as in claim 2 in which said lightly doped silicon is doped to a level between 10 15 ions/cm 3 and 10 18 ions/cm 3 .
Claim 5
Dependent Claim
28 words
Method as in claim 2 in which said doped material is polycrystalline silicon doped to a level between 10 19 ions/cm 3 and 10 22 ions/cm 3 .
Claim 6
Dependent Claim
14 words
Method as in claim 1 in which said sidewall spacers are of silicon dioxide.
Claim 7
Dependent Claim
23 words
Method as in claim 1 in which said refractory metal is taken from the group consisting of platinum, titanium, tungsten, molybdenum, and tantalum.
Claim 8
Dependent Claim
49 words
Method as in claim 1 in which said refractory metal layer has a thickness of 200 nm to 500 nm and said step of heating said integrated circuit structure comprises heating to a temperature of 800° C. to 1000° C. for a time of 30 minutes to 90 minutes.
Claim 9
Dependent Claim
43 words
Method as in claim 1 in which said step of removing unreacted portions of said refractory metal comprises etching with sulfuric acid, 50% by volume, at a temperature between 27° C. and 80° C. for a period of 10 minutes to one hour.
Claim 10
Dependent Claim
31 words
Method as in claim 1 in which said step of oxidizing said refractory metal comprises heating said wafer to a temperature of 800° C. in an atmosphere of water and oxygen.
Claim 11
Dependent Claim
37 words
Method as in claim 1 in which said step of removing oxide using a process which occurs at a constant rate comprises etching said oxide using RIE etching for a time of 30 seconds to 90 seconds.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-27 | 1994-11-26 | 1995-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-27 | 1998-11-26 | 1999-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-27 | 2002-11-26 | 2003-05-28 | $7700.00 | Window Closed / Lapsed |