US4952522A
Expired / Lapsed
US
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Method of fabricating complementary semiconductor integrated circuits devices having an increased immunity to latch-up
Assignee: Mitsubishi Electric Corp
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Filing: 1988-06-28
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Granted: 1990-08-28
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Expires: 2008-06-28
Abstract
Abstract A novel method for making complementary semiconductor IC devices is described. The method includes the steps of: preparing a N-type semiconductor substrate; preparing a first mask for forming a P-well in the N-type substrate; forming the P-well in the N-type substrate using the first mask; preparing a second mask for forming a first P-type diffusion regions in the substrate and in the P-well; preparing a third mask for forming N-type diffusion regions in the substrate and in the P-well; preparing a fourth mask for forming a second P-type diffusion regions in the unoccupied areas of the N-type substrate and the P-well by carrying out reversing, AND and OR processing of the first, second and third masks, and forming the P-type diffusion regions in the prescribed areas of the substrate and the P-well by placing the fourth mask on the substrate.
Inventors
- 👤 Akira Yamada
- 👤 Tsunenori Umeki
- 👤 Masatoshi Aikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:14
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10P; H10P76/00; H10P76/20; H10P76/204; H10P76/2041; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
425 words
A method of fabricating a complementary semiconductor integrated circuit device comprising the steps of: preparing a semiconductor substrate which has a major surface and contains impurities of a first conductivity type having a predetermined concentration; preparing a first mask having a first mask area for defining a first impurity region of a second conductivity type in said major surface of said substrate, said first mask area comprising a masked area and an unmasked area; forming said first impurity region of the second conductivity type and having a predetermined impurity concentration in the predetermined area of said major surface of said substrate by applying said first mask at a predetermined location on said substrate, the area of said major surface of said substrate other than said first impurity region of the second conductivity type constituting a first impurity region of the first conductivity type; preparing a second mask having a second mask area for defining a second impurity region of the second conductivity type and a third impurity region of the second conductivity type in first impurity region of the first conductivity type and said first impurity region of the second conductivity type, respectively, said second mask area comprising a masked area and unmasked area; preparing a third mask having a third mask area for defining a second impurity region of the first conductivity type within said first impurity region of the first conductivity type in juxtaposition with said second impurity region of the second conductivity type, and for defining a third impurity region of the first conductivity type within said first impurity region of the second conductivity type in juxtaposition with said third impurity region of the second conductivity type, said third mask area comprising a masked area and unmasked area; preparing a complement or negative mask of said third mask wherein the relation between the masked and unmasked areas are reversed with respect to that of said third mask; preparing a fourth mask having an unmasked area jointly defined by said unmasked areas of said first and second masks, and a masked area defined by said negative mask of said third mask; forming a second impurity region of the second conductivity type within said first impurity region of the first conductivity type, and third and fourth impurity regions of second conductivity type within said first impurity region of second conductivity type by placing said fourth mask at a predetermined location on said major surface of said substrate, whereby said first impurity region of second conductivity type is made to have a reduced electrical resistance.
Claim 2
Independent Claim
425 words
A method of fabricating a complementary semiconductor integrated circuit device comprising the steps of: preparing a semiconductor substrate which has a major surface and contains impurities of a first conductivity type having a predetermined concentration; preparing a first mask having a first mask area for defining a first impurity region of a second conductivity type in said major surface of said substrate, said first mask area comprising a masked area and an unmasked area; forming said first impurity region of the second conductivity type and having a predetermined impurity concentration in the predetermined area of said major surface of said substrate by applying said first mask at a predetermined location on said substrate, the area of said major surface of said substrate other than said first impurity region of the second conductivity type constituting a first impurity region of the first conductivity type; preparing a second mask having a second mask area for defining a second impurity region of the second conductivity type and a third impurity region of the second conductivity type in first impurity region of the first conductivity type and said first impurity region of the second conductivity type, respectively, said second mask area comprising a masked area and unmasked area; preparing a third mask having a third mask area for defining a second impurity region of the first conductivity type within said first impurity region of the first conductivity type in juxtaposition with said second impurity region of the second conductivity type, and for defining a third impurity region of the first conductivity type within said first impurity region of the second conductivity type in juxtaposition with said third impurity region of the second conductivity type, said third mask area comprising a masked area and unmasked area; preparing a complement or negative mask of said third mask wherein the relation between the masked and unmasked areas are reversed with respect to that of said third mask; preparing a fourth mask having an unmasked area jointly defined by said unmasked areas of said first and second masks, and a masked area defined by said negative mask of said third mask; forming a second impurity region of the second conductivity type within said first impurity region of the first conductivity type, and third and fourth impurity regions of second conductivity type within said first impurity region of second conductivity type by placing said fourth mask at a predetermined location on said major surface of said substrate, whereby said first impurity region of second conductivity type is made to have a reduced electrical resistance.
Claim 3
Dependent Claim
202 words
A method of fabricating a complementary semiconductor integrated circuit device according to claim 1 further including the steps of: preparing a complement or negative mask of said first mask where the relation between the masked and unmasked areas in the mask area is reversed and the unmasked area is expanded; preparing a negative mask of said second mask-wherein the relation between the masked and unmasked areas in the mask area is reversed; preparing a fifth mask having a masked area jointly defined by said negative mask of said first mask and said negative masks of said second mask and an unmasked area defined by said third mask; forming a second impurity region of first conductivity type and a fourth impurity region of a first conductivity type within said first impurity region of first conductivity type in an area where said second impurity region of second conductivity type has not been formed, and a third impurity region of first conductivity type within said first impurity region of second conductivity type in an area where said third, fourth impurity regions of second conductivity type have not been formed, whereby said first region of first conductivity type is made to have a reduced electrical resistance.
Claim 4
Dependent Claim
34 words
A method of fabricating a complementary semiconductor integrated circuit device according to claim 2 wherein said masked and unmasked areas in said first, second, third, fourth and fifth masks are defined by a computer.
Claim 5
Dependent Claim
43 words
A method of fabricating a complementary semiconductor integrated circuit device according to claim 3 wherein said computer has a pattern reversing function and said negative masks of said first, second and third masks are prepared by said pattern reversing function of said computer.
Claim 6
Dependent Claim
44 words
A method of fabricating a complementary semiconductor integrated circuit device according to claim 4 wherein said computer has AND and OR functions, and said masked and unmasked areas of said fourth and fifth masks are defined by said AND, OR functions of said computers.
Claim 7
Dependent Claim
50 words
A method of fabricating a complementary semiconductor integrated circuit device according to claim 2 further comprising the steps of: forming a thin oxide layer over said second, third, and fourth impurity regions of said first conductivity type and over said second, third and fourth impurity regions of second conductivity type.
Claim 8
Dependent Claim
102 words
A method of fabricating a complementary semiconductor integrated circuit device according to claim 6, wherein said thin oxide layer is formed by a mask, said step of preparing said mask for forming said thin oxide layer comprising the steps of: preparing a sixth mask having a mask area defined jointly by said unmasked areas of said first mask and the negative mask of said fifth mask, or defined jointly by unmasked areas of said negative mask of said first mask having undersized unmasked area and the negative mask of said fourth masks, or defined by the unmasked area of said second mask.
Claim 9
Dependent Claim
43 words
A method of fabricating a complementary semiconductor integrated circuit device according to claim 7 further including the steps of: forming an insulating layer on a predetermined area of said major surface of said substrate, and forming a conductor layer on said insulating layer.
Claim 10
Dependent Claim
93 words
A method of fabricating a complementary semiconductor integrated circuit device according to claim 8 further comprising the steps of: forming said second impurity region of first conductivity type; forming said thin oxide layer on said major surface of said substrate using said sixth mask; forming said conductor layer on said major surface of said substrate; and forming on said thin oxide layer on said second, third and fourth impurity regions of first conductivity type, and on said second, third and fourth regions of second conductivity type by utilizing said fourth and fifth masks.
Claim 11
Dependent Claim
25 words
A method of fabricating a complementary semiconductor integrated circuit device according to claim 8 wherein said complementary semiconductor integrated circuit device comprises a CMOS inverter.
Claim 12
Dependent Claim
35 words
A method of fabricating a complementary semiconductor integrated circuit device according to claim 10 wherein said masked and unmasked areas in said first, second, third, fourth, fifth, and sixth masks are defined by a computer.
Claim 13
Dependent Claim
44 words
A method of fabricating a complementary semiconductor integrated circuit device according to claim 11 wherein said computer has a pattern reversing function, and said negative masks of said first, second, third and fifth masks are prepared by said pattern reversing function of said computer.
Claim 14
Dependent Claim
45 words
A method of fabricating a complementary semiconductor integrated circuit device according to claim 12 wherein said computer has AND and OR functions, and said masked and unmasked area of said fourth, fifth and sixth masks are defined by said AND, OR functions of said computers.
References Cited (Backward Citations)
US3598604A
Cited
JPS5425177A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-08-27 | 1994-02-26 | 1994-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-27 | 1998-02-26 | 1998-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-27 | 2002-02-26 | 2002-08-28 | $7700.00 | Window Closed / Lapsed |