US3598604A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process of producing an array of integrated circuits on semiconductor substrate
Assignee: International Business Machines Corp
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Filing: 1968-11-19
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Granted: 1971-08-10
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Expires: 1988-11-19
Abstract
Abstract YIELD IN SEMICONDUCTOR MANUFACTURING PROCESSES WHEREIN A PLURALITY OF MASKS ARE USED FOR DIFFERENT PROCESSING STEPS TO EXPOSE PHOTORESIST IN ARRAYS OF PATTERNS FOR SEMICONDUCTOR CIRCUITS ON A WAFER MAY BE MAXIMIZED BY OVERLAYING DEFECTS IN THE MASKS. THIS MAY BE DONE BY COMBINING ONE MASK FOR EACH PROCESSING STEP IN VARIOUS COMBINATIONS, THEN SELECTING THE COMBINATION FOR USE WHICH WILL MINIMIZE THE NUMBER OF DEFECTIVE INTEGRATED CIRCUITS IN THE ARRAY.
Inventors
- 👤 Arthur H De Puy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 06:47
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/61; D; D06; D06F; D06F15/00; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0158; H10P95/00; Y; Y10; Y10S; Y10S438/00; Y10S438/942
Claims Analysis
Total Claims: 0
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References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-09 | 1975-02-08 | 1975-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-09 | 1979-02-08 | 1979-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-09 | 1983-02-08 | 1983-08-10 | $7700.00 | Window Closed / Lapsed |