US5097422A
Expired / Lapsed
US
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Method and apparatus for designing integrated circuits
Assignee: Cascade Design Automation Corp
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Filing: 1989-06-29
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Granted: 1992-03-17
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Expires: 2009-06-29
Abstract
Abstract A method and apparatus for determining integrated circuit layouts from a virtual circuit description and specification of a technology. Starting with high-level descriptions of a circuit, a virtual geometric description of the circuit is developed using a virtual grid described in terms of reference points relative to a substrate surface. The relationships among the reference points are expressed as fractions of variables that can also be used to define the design rules. When the technology is specified, the relationships among the reference points is determined, as in the layout of the integrated circuit.
Inventors
- 👤 II Ludlow V. Corbin
- 👤 Steven G. Danielson
- 👤 Richard E. Oettel
- 👤 Mark E. Rossman
- 👤 James E. Thiele
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:05
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
144 words
A method of designing the layout of the physical geometry of an integrated circuit, the layout comprising a plurality of layers formed on a surface of a substrate, each layer including a pattern of a material having predetermined electrical properties, said method comprising: identifying a plurality of design rule variables, each design rule variable relating to at least one geometric constraint with respect to a pattern on at least one of said layers; defining first and second virtual coordinate axes with respect to the surface of said substrate; and defining the position of at least a portion of the pattern in at least one of said layers relative to at least one of said coordinate axes as a function of at least one of said design rule variables and the position of at least a portion of a pattern in another of said layers.
Claim 2
Independent Claim
144 words
A method of designing the layout of the physical geometry of an integrated circuit, the layout comprising a plurality of layers formed on a surface of a substrate, each layer including a pattern of a material having predetermined electrical properties, said method comprising: identifying a plurality of design rule variables, each design rule variable relating to at least one geometric constraint with respect to a pattern on at least one of said layers; defining first and second virtual coordinate axes with respect to the surface of said substrate; and defining the position of at least a portion of the pattern in at least one of said layers relative to at least one of said coordinate axes as a function of at least one of said design rule variables and the position of at least a portion of a pattern in another of said layers.
Claim 3
Dependent Claim
56 words
The method of claim 1, further including the step of defining a module specification which describes the function and technology of said integrated circuit, and wherein said step of defining the positions of at least a portion of the pattern in at least one of said layers is performed as a function of said module specification.
Claim 4
Dependent Claim
37 words
The method of claim 1, further including the step of generating a simulation model of said integrated circuit to mathematically simulate said integrated circuit, thereby allowing the performance of said integrated circuit to be verified and tested.
Claim 5
Dependent Claim
26 words
The method of claim 1, further including the step of plotting the layout of said integrated circuit after the positions of said patterns have been defined.
Claim 6
Dependent Claim
132 words
The method of claim 1 wherein said first and second virtual coordinate axes have an origin and a predetermined relationship to the surface of said substrate, and wherein said step of defining the position of at least a portion of the pattern in at least one of said layers includes the steps of: defining landmark points among said pattern by expressing the coordinates of said pattern in terms of reference points along said first and second virtual coordinate axes, the definition of at least one reference point on said layer being given relative to said origin as a function of a reference point on another of said layers and a set of said design rule variables; and substituting respective values for said design rule variables into the definitions of said reference points.
Claim 7
Independent Claim
194 words
A method of designing the layout of the physical geometry of an integrated circuit, the layout comprising a plurality of layers formed on a surface of a substrate, each layer including a pattern of a material having predetermined electrical properties, the pattern of materials interacting to form elemental electrical circuit features, such as transistors, contacts, and signal traces, which interfit with each other, at least one elemental electrical circuit feature being subject to at least one geometric constraint relative to another elemental electrical feature, the method comprising the steps of: identifying a plurality of design rule variables, each design rule variable relating to at least one of said geometric constraints; defining first and second virtual coordinate axes with respect to the surface of said substrate; and defining the positions of at least a portion of some of said elemental electrical circuit features in at least one of said integrated circuit layers relative to at least one of said coordinate axes as a function of at least one of said design rule variables and the position of at least one portion of another of said elemental electrical circuit features on the same integrated circuit layer.
Claim 8
Independent Claim
194 words
A method of designing the layout of the physical geometry of an integrated circuit, the layout comprising a plurality of layers formed on a surface of a substrate, each layer including a pattern of a material having predetermined electrical properties, the pattern of materials interacting to form elemental electrical circuit features, such as transistors, contacts, and signal traces, which interfit with each other, at least one elemental electrical circuit feature being subject to at least one geometric constraint relative to another elemental electrical feature, the method comprising the steps of: identifying a plurality of design rule variables, each design rule variable relating to at least one of said geometric constraints; defining first and second virtual coordinate axes with respect to the surface of said substrate; and defining the positions of at least a portion of some of said elemental electrical circuit features in at least one of said integrated circuit layers relative to at least one of said coordinate axes as a function of at least one of said design rule variables and the position of at least one portion of another of said elemental electrical circuit features on the same integrated circuit layer.
Claim 9
Dependent Claim
51 words
The method of claim 6, further including the step of defining a module specification which describes the function and technology of said integrated circuit, and wherein said step of defining the positions of at least some of said elemental electrical circuit features is performed as a function of said module specification.
Claim 10
Dependent Claim
37 words
The method of claim 6, further including the step of generating a simulation model of said integrated circuit to mathematically simulate said integrated circuit, thereby allowing the performance of said integrated circuit to be verified and tested.
Claim 11
Dependent Claim
29 words
The method of claim 6, further including the step of plotting the layout of said integrated circuit after the positions of said elemental electrical circuit features have been defined.
Claim 12
Dependent Claim
138 words
The method of claim 6 wherein said first and second virtual coordinate axes have an origin and a predetermined relationship to the surface of said substrate, and wherein said step of defining the position of at least some of said elemental electrical circuit features in at least one of said layers includes the steps of: defining landmark points among said elemental electrical circuit features by expressing the coordinates of said circuit features in terms of reference points along said first and second virtual coordinate axes, the definition of at least one reference point on said layer being given relative to said origin as a function of a reference point on another of said layers and a set of said design rule variables; and substituting respective values for said design rule variables into the definitions of said reference points.
Claim 13
Independent Claim
170 words
An apparatus for designing the layout of the physical geometry of an integrated circuit, the layout comprising a plurality of layers formed on a surface of a substrate, each layer including a pattern of a material having predetermined electrical properties, said apparatus comprising: input means for accepting a plurality of values corresponding to respective design rule variables, each design rule variable relating to at least one geometric constraint with respect to at least one of said layers; means for defining first and second virtual coordinate axes with respect to the surface of said substrate; and memory means for storing said plurality of values and said first and second virtual coordinate axes; and processing means for defining the position of at least a portion of the pattern in at least one of said layers relative to at least one of said coordinate axes as a function of at least one of said design rule variables and the position of at least a portion of a pattern in another of said layers.
Claim 14
Independent Claim
170 words
An apparatus for designing the layout of the physical geometry of an integrated circuit, the layout comprising a plurality of layers formed on a surface of a substrate, each layer including a pattern of a material having predetermined electrical properties, said apparatus comprising: input means for accepting a plurality of values corresponding to respective design rule variables, each design rule variable relating to at least one geometric constraint with respect to at least one of said layers; means for defining first and second virtual coordinate axes with respect to the surface of said substrate; and memory means for storing said plurality of values and said first and second virtual coordinate axes; and processing means for defining the position of at least a portion of the pattern in at least one of said layers relative to at least one of said coordinate axes as a function of at least one of said design rule variables and the position of at least a portion of a pattern in another of said layers.
Claim 15
Dependent Claim
38 words
The apparatus of claim 11, further including a simulation model generator for generating a mathematical model of said integrated circuit to simulate said integrated circuit, thereby allowing the performance of said integrated circuit to be verified and tested.
Claim 16
Dependent Claim
31 words
The apparatus of claim 11, further including means operatively connected to said processing means for plotting the layout of said integrated circuit after the positions of said patterns have been defined.
Claim 17
Independent Claim
219 words
An apparatus for designing the layout of the physical geometry of an integrated circuit, the layout comprising a plurality of layers formed on a surface of a substrate, each layer including a pattern of a material having predetermined electrical properties, the patterns of materials interacting to form elemental electrical circuit features such as transistors, contacts, and signal traces, which interfit with each other, at least one elemental electrical circuit feature being subject to at least one geometric constraint relative to another elemental electrical feature, said apparatus comprising: input means for accepting a plurality of values corresponding to respective design rule variables,, each design rule variable relating to at least one of said geometric constraints; means for defining first and second virtual coordinate axes with respect to the surface of said substrate; memory means for storing said plurality of values and said first and second virtual coordinate axes; and processing means for defining the positions of at least a portion of some of said elemental electrical circuit features in at least one of said integrated circuit layers relative to at least one of said coordinate axes as a function of at least one of said design rule variables and the position of at least one portion of another of said elemental electrical circuit features on the same integrated circuit layer.
Claim 18
Independent Claim
219 words
An apparatus for designing the layout of the physical geometry of an integrated circuit, the layout comprising a plurality of layers formed on a surface of a substrate, each layer including a pattern of a material having predetermined electrical properties, the patterns of materials interacting to form elemental electrical circuit features such as transistors, contacts, and signal traces, which interfit with each other, at least one elemental electrical circuit feature being subject to at least one geometric constraint relative to another elemental electrical feature, said apparatus comprising: input means for accepting a plurality of values corresponding to respective design rule variables,, each design rule variable relating to at least one of said geometric constraints; means for defining first and second virtual coordinate axes with respect to the surface of said substrate; memory means for storing said plurality of values and said first and second virtual coordinate axes; and processing means for defining the positions of at least a portion of some of said elemental electrical circuit features in at least one of said integrated circuit layers relative to at least one of said coordinate axes as a function of at least one of said design rule variables and the position of at least one portion of another of said elemental electrical circuit features on the same integrated circuit layer.
Claim 19
Dependent Claim
38 words
The apparatus of claim 14, further including a simulation model generator for generating a mathematical model of said integrated circuit to simulate said integrated circuit, thereby allowing the performance of said integrated circuit to be verified and tested.
Claim 20
Dependent Claim
34 words
The apparatus of claim 14, further including means operatively connected to said processing means for plotting the layout of said integrated circuit after the positions of said elemental electrical circuit features have been defined.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-17 | 1995-09-16 | 1996-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-17 | 1999-09-16 | 2000-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-17 | 2003-09-16 | 2004-03-17 | $7700.00 | Window Closed / Lapsed |