USH354H
Expired / Lapsed
US
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Linear algorithm for non-linear interpolation for computer aided designs
Assignee: United States Department of the Army
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Filing: 1986-04-04
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Granted: 1987-10-06
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Expires: 2006-04-04
Abstract
Abstract The linear algorithm described differs from other artificial intelligence ograms in its operation over a continuous representation. In the algorithm, the size of the exponent is tied to the magnitude of the learning base employed, and the design thus becomes more selective as the learning base grows. With it, "run time" and "chip size" can be analyzed in substantially linear time.
Inventors
- 👤 Stuart H. Rubin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 10:39
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
171 words
A computer process for the automatic layout of multiport, two-dimensional microcircuits comprising the steps of: (a) defining a general microcircuit layout including an x-y orthogonal grid, logic cell geometry and relative cell placement, and node interconnections of logic cells; (b) generating an initial placement surface of logic cell rows by establishing cell placements on said orthogonal grid; (c) exchanging cell pair locations according to multiple criteria in order to optimize cell placement; (d) exchanging node-connected cell pairs along cell rows to thereby reduce the distance to the nearest connected cells; (e) establishing routing for pin-to-pin connections; (f) establishing subchip interior routing; (g) establishing routing from cell rows to peripheral power connectors; (h) analyzing routing output for translation to a computer graphics language which is suitable for describing the fabrication layout of the circuit module; (i) creating power bus routes; (j) translating placement and connection data into said computer graphics language; and (k) predicting from the microcircuit layout parameters the microcircuit design or run time and the probable size of the microcircuit.
Claim 2
Dependent Claim
171 words
A computer process for the automatic layout of multiport, two-dimensional microcircuits comprising the steps of: (a) defining a general microcircuit layout including an x-y orthogonal grid, logic cell geometry and relative cell placement, and node interconnections of logic cells; (b) generating an initial placement surface of logic cell rows by establishing cell placements on said orthogonal grid; (c) exchanging cell pair locations according to multiple criteria in order to optimize cell placement; (d) exchanging node-connected cell pairs along cell rows to thereby reduce the distance to the nearest connected cells; (e) establishing routing for pin-to-pin connections; (f) establishing subchip interior routing; (g) establishing routing from cell rows to peripheral power connectors; (h) analyzing routing output for translation to a computer graphics language which is suitable for describing the fabrication layout of the circuit module; (i) creating power bus routes; (j) translating placement and connection data into said computer graphics language; and (k) predicting from the microcircuit layout parameters the microcircuit design or run time and the probable size of the microcircuit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-05 | 1991-04-06 | 1991-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-05 | 1995-04-06 | 1995-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-05 | 1999-04-06 | 1999-10-06 | $7700.00 | Window Closed / Lapsed |