Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells

Claim 1

A method of forming an SRAM (Static Random Access Memory), a floating gate memory, and a logic device on a single semiconductor substrate, in a first memory region, a second memory region, and a logic region, respectively, comprising the steps of: providing a semiconductor substrate; forming field isolation regions in said semiconductor substrate; forming a gate oxide over said substrate between said field isolation regions; depositing a first polysilicon layer over said gate oxide; patterning said first polysilicon layer, comprising: forming gates over a portion of said gate oxide a gate being formed in said first and second memory regions and said logic region, forming a polysilicon interconnect over a portion of said field isolation regions, only in said first memory region; and forming a floating gate over a field oxide region in said second memory region; forming lightly doped drain (LDD) active regions in said substrate, adjacent to each said gates over a portion of said gate oxide; forming insulating spacers on sidewalls of said gates, polysilicon interconnect and said floating gate; completing formation of said active regions by a heavy ion implant; removing said insulating spacers from the sidewalls of said polysilicon interconnect; forming a first interpoly oxide over said floating gate and over said gate in said second memory region, whereby protected gate areas are formed; forming a layer of titanium silicide over said gates, polysilicon interconnect and active regions, except over said protected gate areas, whereby said titanium silicide electrically connects said polysilicon interconnect and said active regions in said first memory region; forming a second interpoly oxide over said semiconductor substrate; forming an opening in said second interpoly oxide over said polysilicon interconnect; depositing a second layer of polysilicon over said substrate; and patterning said second layer of polysilicon to form a control gate over said floating gate, and to form a load resistor for said SRAM.

Claim 2

A method of forming an SRAM (Static Random Access Memory), a floating gate memory, and a logic device on a single semiconductor substrate, in a first memory region, a second memory region, and a logic region, respectively, comprising the steps of: providing a semiconductor substrate; forming field isolation regions in said semiconductor substrate; forming a gate oxide over said substrate between said field isolation regions; depositing a first polysilicon layer over said gate oxide; patterning said first polysilicon layer, comprising: forming gates over a portion of said gate oxide a gate being formed in said first and second memory regions and said logic region, forming a polysilicon interconnect over a portion of said field isolation regions, only in said first memory region; and forming a floating gate over a field oxide region in said second memory region; forming lightly doped drain (LDD) active regions in said substrate, adjacent to each said gates over a portion of said gate oxide; forming insulating spacers on sidewalls of said gates, polysilicon interconnect and said floating gate; completing formation of said active regions by a heavy ion implant; removing said insulating spacers from the sidewalls of said polysilicon interconnect; forming a first interpoly oxide over said floating gate and over said gate in said second memory region, whereby protected gate areas are formed; forming a layer of titanium silicide over said gates, polysilicon interconnect and active regions, except over said protected gate areas, whereby said titanium silicide electrically connects said polysilicon interconnect and said active regions in said first memory region; forming a second interpoly oxide over said semiconductor substrate; forming an opening in said second interpoly oxide over said polysilicon interconnect; depositing a second layer of polysilicon over said substrate; and patterning said second layer of polysilicon to form a control gate over said floating gate, and to form a load resistor for said SRAM.

Claim 11

A method of forming a local interconnect in an SRAM simultaneously with the formation of a salicide in logic devices on the same semiconductor substrate, wherein a floating gate memory is also formed, comprising the steps of: providing a semiconductor substrate having MOS (Metal Oxide Semiconductor) transistors formed therein, separated by field isolation regions, one of said transisiors formed in a floating gate memory region, each said transistor comprising a gate overlying a gate oxide and having source and drain regions in said substrate, with spacers on the sidewalls of said gates, wherein a portion of said field oxide regions in said SRAM have a polysilicon interconnect, with sidewall spacers, thereover, and wherein a floating gate is formed over a field isolation region in said floating gate memory region; removing said sidewall spacers from said polysilicon interconnect; forming a first interpoly oxide over said floating gate and over said gate in said floating gate memory region; depositing a layer of titanium over said semiconductor substrate; and forming said salicide over said gates, said source and drain regions, and said polysilicon interconnect, and whereby said local interconnect is formed connecting said polysilicon interconnect to one of said source regions.

Claim 12

A method of forming a local interconnect in an SRAM simultaneously with the formation of a salicide in logic devices on the same semiconductor substrate, wherein a floating gate memory is also formed, comprising the steps of: providing a semiconductor substrate having MOS (Metal Oxide Semiconductor) transistors formed therein, separated by field isolation regions, one of said transisiors formed in a floating gate memory region, each said transistor comprising a gate overlying a gate oxide and having source and drain regions in said substrate, with spacers on the sidewalls of said gates, wherein a portion of said field oxide regions in said SRAM have a polysilicon interconnect, with sidewall spacers, thereover, and wherein a floating gate is formed over a field isolation region in said floating gate memory region; removing said sidewall spacers from said polysilicon interconnect; forming a first interpoly oxide over said floating gate and over said gate in said floating gate memory region; depositing a layer of titanium over said semiconductor substrate; and forming said salicide over said gates, said source and drain regions, and said polysilicon interconnect, and whereby said local interconnect is formed connecting said polysilicon interconnect to one of said source regions.