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EP0469935A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method for manufacturing a semiconductor memory device

Assignee: Sharp Corp
•
Filing: 1991-08-05
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Granted: —
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Expires: 2011-08-05
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Abstract

Abstract A method for manufacturing a semiconductor device including steps of (i) laminating a first insulating film over a semiconductor substrate having a plurality of gate electrodes, on which side walls are at least formed, through capacitor formation regions, removing the first insulating film in the capacitor formation region so as to form a direct contact, and laminating a first conductive film over the semiconductor substrate including the residual first insulating film, (ii) removing the first conductive film with remaining at least in the capacitor formation region, (iii) sequentially laminating over the semiconductor substrate including the residual first conductive film (a) a second insulating film, a second conductive film and a third insulating film, or (b) a second insulating film and a second conductive film, and then laminating a resist layer over the whole surface, and (iv) patterning the resist layer and removing with the use of a resist pattern (a) the third insulating film, second conductive film, second insulating film and first conductive film, or (b) the second conductive film, second insulating film and first conductive film, so that the capacitor electrodes of a FEC type DRAM cell including a capacitor upper electrode, a capacitor insulating film and a capacitor lower electrode can be formed in the capacitor formation region.

Inventors

  • 👤 Narakazu Shimomura
  • 👤 Masahiro Hasegawa

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-05 19:52
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/60; H10D1/68; H10W; H10W20/00; H10W20/01; H10W20/021; Y; Y10; Y10S; Y10S438/00; Y10S438/98

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 210 words
A method for manufacturing a semiconductor device comprising steps of; (i) laminating a first insulating film over a semiconductor substrate having a plurality of gate electrodes, on which side walls are at least formed, through capacitor formation regions, removing the first insulating film in the capacitor formation region so as to form a direct contact, and laminating a first conductive film over the semiconductor substrate including the residual first insulating film, (ii) removing the first conductive film with remaining at least in the capacitor formation region, (iii) sequentially laminating over the semiconductor substrate including the residual first conductive film (a) a second insulating film, a second conductive film and a third insulating film, or (b) a second insulating film and a second conductive film, and then laminating a resist layer over the whole surface, and (iv) patterning the resist layer and removing with the use of a resist pattern (a) the third insulating film, second conductive film, second insulating film and first conductive film, or (b) the second conductive film, second insulating film and first conductive film, so that the capacitor electrodes of a FEC type DRAM cell comprising a capacitor upper electrode, a capacitor insulating film and a capacitor lower electrode can be formed in the capacitor formation region.
Claim 2
Dependent Claim 62 words
A method for manufacturing a semiconductor device according to Claim 1, wherein a first conductive film portion is formed by etching the first conductive film by an anisotropic etching method such as RIE with the use of a photoresist pattern formed by a projection and exposure method so as to expose the same in regions other than a contact hole formation region.
Claim 3
Dependent Claim 41 words
A method for manufacturing a semiconductor device according to Claim 1, wherein a local wiring is patterned in order to electrically connect the capacitor upper electrode to a memory cell transistor in the contact hole formation region including a contact hole.
Claim 4
Independent Claim 56 words
A method of forming a capacitor for a FEC type DRAM cell, wherein the same photoresist pattern or SiO₂ pattern is used as an etching mask to process a three-layer film comprising a capacitor upper electrode, a capacitor insulating film and a capacitor lower electrode by an anisotropic etching method such as reactive ion etching (RIE).
Claim 5
Independent Claim 47 words
A method of forming a capacitor for a FEC type DRAM cell in which a single mask is used for forming a capacitor lower electrode, a capacitor insulating film and a capacitor upper electrode, the capacitor upper and lower electrodes being simultaneously processed by said single mask.

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