US5595944A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor and process for fabricating the same
Assignee: Semiconductor Energy Laboratory Co Ltd
•
Filing: 1994-12-21
•
Granted: 1997-01-21
•
Expires: 2014-12-21
Abstract
Abstract A process for fabricating a thin film transistor, which comprises crystallizing an amorphous silicon film, forming thereon a gate insulating film and a gate electrode, implanting impurities in a self-aligned manner, adhering a coating containing a catalyst element which accelerates the crystallization of the silicon film, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities. Otherwise, the catalyst element can be incorporated into the structure by introducing it into the impurity region by means of ion implantation and the like. Also a process for fabricating a thin film transistor, which comprises forming a gate electrode, a gate insulating film, and an amorphous silicon film on a substrate, implanting impurities into the amorphous silicon film to form source and drain regions as the impurity regions, introducing a catalyst element into the impurity region by adhering a coating containing the catalyst element of by means of ion doping and the like, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities.
Inventors
- 👤 Hongyong Zhang
- 👤 Toru Takayama
- 👤 Yasuhiko Takemura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:54
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0316; H10D30/0321; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/673; H10D30/6731; H10D30/6732; H10D30/6737; H10D30/6739; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10P14/00; H10P14/20; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/38; H10P14/3802; H10P14/3806; H10P30/208
Claims Analysis
Total Claims: 54
Claim 1
Independent Claim
121 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating layer on said gate electrode; forming a semiconductor layer over said gate electrode, said gate electrode insulated from said semiconductor layer by said gate insulating layer interposed therebetween; forming a mask over said semiconductor layer, wherein said mask is formed in a self-alignment manner with respect to said gate electrode; introducing metal ions into a first region of said semiconductor layer in a self-alignment manner with respect to said mask; introducing impurity ions into a second region of said semiconductor layer in a self-alignment manner with respect to said mask to form source and drain regions.
Claim 2
Independent Claim
121 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating layer on said gate electrode; forming a semiconductor layer over said gate electrode, said gate electrode insulated from said semiconductor layer by said gate insulating layer interposed therebetween; forming a mask over said semiconductor layer, wherein said mask is formed in a self-alignment manner with respect to said gate electrode; introducing metal ions into a first region of said semiconductor layer in a self-alignment manner with respect to said mask; introducing impurity ions into a second region of said semiconductor layer in a self-alignment manner with respect to said mask to form source and drain regions.
Claim 3
Dependent Claim
18 words
The method of claim 1 wherein said gate insulating layer is formed by anodic oxidizing said gate electrode.
Claim 4
Dependent Claim
18 words
The method of claim 1 wherein said first region and said second region are identical with each other.
Claim 5
Dependent Claim
20 words
The method of claim 1 wherein said metal is selected from the group consisting of Ni, Fe, Co, and Pt.
Claim 6
Dependent Claim
12 words
The method of claim 1 wherein said mask comprises a photoresist material.
Claim 7
Dependent Claim
11 words
The method of claim 1 wherein said semiconductor layer comprises silicon.
Claim 8
Dependent Claim
67 words
The process of claim 1 comprising the further step of: forming a source region and a drain region and an active area provided between said source region and drain region, wherein said source and drain region contains a catalyst material at a concentration higher than 1×10 17 atoms/cm 3 and said active region contains the catalyst material at a concentration lower than 1×10 17 atoms/cm 3 .
Claim 9
Dependent Claim
26 words
The method of claim 1 wherein said substrate is made of glass, and said mask is formed by exposure from a back of said glass substrate.
Claim 10
Dependent Claim
29 words
The method of claim 1 further comprising the step of annealing said semiconductor layer after introducing said metal ions for crystallizing at least a portion of said semiconductor layer.
Claim 11
Independent Claim
116 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating layer on said gate electrode; forming a semiconductor layer over said gate electrode, said semiconductor layer being insulated from said gate electrode by said gate insulating layer interposed therebetween; forming a mask over said semiconductor layer, wherein said mask is formed in a self-alignment manner with respect to said gate electrode; forming a metal containing film on said semiconductor layer having said mask formed thereon; introducing impurity ions into a first region of said semiconductor layer in a self-alignment manner with respect to said mask to form source and drain regions.
Claim 12
Independent Claim
116 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating layer on said gate electrode; forming a semiconductor layer over said gate electrode, said semiconductor layer being insulated from said gate electrode by said gate insulating layer interposed therebetween; forming a mask over said semiconductor layer, wherein said mask is formed in a self-alignment manner with respect to said gate electrode; forming a metal containing film on said semiconductor layer having said mask formed thereon; introducing impurity ions into a first region of said semiconductor layer in a self-alignment manner with respect to said mask to form source and drain regions.
Claim 13
Dependent Claim
41 words
The method of claim 10 further comprising the step of diffusing said metal or a silicide of said metal from said metal containing film into a second region of said semiconductor layer in a self-alignment manner with respect to said mask.
Claim 14
Dependent Claim
18 words
The method of claim 10 wherein said gate insulating layer is formed by anodic oxidizing said gate electrode.
Claim 15
Dependent Claim
18 words
The method of claim 11 wherein said first region and said second region are identical with each other.
Claim 16
Dependent Claim
20 words
The method of claim 10 wherein said metal is selected from the group consisting of Ni, Fe, Co, and Pt.
Claim 17
Dependent Claim
12 words
The method of claim 10 wherein said mask comprises a photoresist material.
Claim 18
Dependent Claim
14 words
The method of claim 10 wherein said metal containing film comprises a metal silicide.
Claim 19
Dependent Claim
11 words
The metal of claim 10 wherein said semiconductor layer comprises silicon.
Claim 20
Dependent Claim
67 words
The process of claim 10 comprising the further step of: forming a source region and a drain region and an active area provided between said source region and drain region, wherein said source and drain region contains a catalyst material at a concentration higher than 1×10 17 atoms/cm 3 and said active region contains the catalyst material at a concentration lower than 1×10 17 atoms/cm 3 .
Claim 21
Dependent Claim
26 words
The method of claim 10 wherein said substrate is made of glass and said mask is formed by exposure from the back of said glass substrate.
Claim 22
Dependent Claim
30 words
The method of claim 10 further comprising the step of annealing said semiconductor layer after forming said metal containing film for crystallizing at least a portion of said semiconductor layer.
Claim 23
Independent Claim
117 words
A method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor layer on a substrate; forming a gate insulating layer on said semiconductor layer; forming a gate electrode over said semiconductor layer on said gate insulating film; patterning said gate insulating layer with said gate electrode as a mask so that a surface of said semiconductor is exposed at a portion other than that below said gate electrode; introducing impurity ions into a first region of said semiconductor layer with said gate electrode as a mask to form source and drain regions; disposing a metal containing film in contact with the exposed surface of said semiconductor layer having said gate electrode as a mask.
Claim 24
Independent Claim
117 words
A method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor layer on a substrate; forming a gate insulating layer on said semiconductor layer; forming a gate electrode over said semiconductor layer on said gate insulating film; patterning said gate insulating layer with said gate electrode as a mask so that a surface of said semiconductor is exposed at a portion other than that below said gate electrode; introducing impurity ions into a first region of said semiconductor layer with said gate electrode as a mask to form source and drain regions; disposing a metal containing film in contact with the exposed surface of said semiconductor layer having said gate electrode as a mask.
Claim 25
Dependent Claim
27 words
The method of claim 21 further comprising the step of diffusing said metal or a silicide of said metal into a second region of said semiconductor layer.
Claim 26
Dependent Claim
18 words
The method of claim 22 wherein said first region and said second region are identical with each other.
Claim 27
Dependent Claim
24 words
The method of claim 21 wherein said impurity ions are introduced through said gate insulating layer into said semiconductor layer prior to said patterning.
Claim 28
Dependent Claim
20 words
The method of claim 21 wherein said metal is selected from the group consisting of Ni, Fe, Co, and Pt.
Claim 29
Dependent Claim
14 words
The method of claim 21 wherein said metal containing film comprises a metal silicide.
Claim 30
Dependent Claim
11 words
The method of claim 21 wherein said semiconductor layer comprises silicon.
Claim 31
Dependent Claim
67 words
The process of claim 21 comprising the further step of: forming a source region and a drain region and an active area provided between said source region and drain region, wherein said source and drain region contains a catalyst material at a concentration higher than 1×10 17 atoms/cm 3 and said active region contains the catalyst material at a concentration lower than 1×10 17 atoms/cm 3 .
Claim 32
Dependent Claim
30 words
The method of claim 21 further comprising the step of annealing said semiconductor layer after disposing said metal containing film for crystallizing at least a portion of said semiconductor layer.
Claim 33
Independent Claim
79 words
A method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor layer on a substrate; forming a gate insulating film on said semiconductor layer; forming a gate electrode on said gate insulating film; introducing impurity ions into a first region of said semiconductor layer to form source and drain regions with said gate electrode as a mask; and introducing metal ions into a second region of said semiconductor layer with said gate electrode as a mask.
Claim 34
Independent Claim
79 words
A method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor layer on a substrate; forming a gate insulating film on said semiconductor layer; forming a gate electrode on said gate insulating film; introducing impurity ions into a first region of said semiconductor layer to form source and drain regions with said gate electrode as a mask; and introducing metal ions into a second region of said semiconductor layer with said gate electrode as a mask.
Claim 35
Dependent Claim
38 words
The method of claim 30 further comprising the step of anodizing said gate electrode prior to the introduction of said impurity ions and said metal ions in order to form an anodic oxide layer on said gate electrode.
Claim 36
Dependent Claim
18 words
The method of claim 30 wherein said first region and said second region are identical with each other.
Claim 37
Dependent Claim
20 words
The method of claim 30 wherein said metal is selected from the group consisting of Ni, Fe, Co, and Pt.
Claim 38
Dependent Claim
11 words
The method of claim 30 wherein said semiconductor layer comprises silicon.
Claim 39
Dependent Claim
28 words
The method of claim 30 further comprising the step of annealing said semiconductor layer after introducing metal ions for crystallizing at least a portion of said semiconductor layer.
Claim 40
Independent Claim
138 words
A method of manufacturing an insulating gate field effect transistor comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating layer on said gate electrode; forming a semiconductor layer over said gate electrode, said semiconductor layer being insulated from said gate electrode by said gate insulating layer interposed therebetween; forming a mask over said semiconductor layer, wherein said mask is formed in a self-alignment manner with respect to said gate electrode; forming a metal containing film on said semiconductor layer having said mask formed thereon in order to introduce said metal into a region of said semiconductor layer; removing a portion of said metal at least located on said mask; and introducing impurity ions into said semiconductor layer in a self-alignment manner with respect to said mask to form source and drain regions.
Claim 41
Independent Claim
138 words
A method of manufacturing an insulating gate field effect transistor comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating layer on said gate electrode; forming a semiconductor layer over said gate electrode, said semiconductor layer being insulated from said gate electrode by said gate insulating layer interposed therebetween; forming a mask over said semiconductor layer, wherein said mask is formed in a self-alignment manner with respect to said gate electrode; forming a metal containing film on said semiconductor layer having said mask formed thereon in order to introduce said metal into a region of said semiconductor layer; removing a portion of said metal at least located on said mask; and introducing impurity ions into said semiconductor layer in a self-alignment manner with respect to said mask to form source and drain regions.
Claim 42
Independent Claim
120 words
A method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor layer on a substrate; forming a gate insulating layer on said semiconductor layer; forming a gate electrode over said semiconductor layer on said gate insulating film; patterning said gate insulating layer with said gate electrode as a mask so that a surface of said semiconductor is exposed at a portion other than that below said gate electrode; introducing impurity ions into said semiconductor layer with said gate electrode as a mask to form source and drain regions; disposing a metal containing film over said semiconductor layer having said gate electrode formed thereon; and removing a portion of said metal containing film located over said gate electrode.
Claim 43
Independent Claim
120 words
A method of manufacturing a semiconductor device comprising the steps of: forming a semiconductor layer on a substrate; forming a gate insulating layer on said semiconductor layer; forming a gate electrode over said semiconductor layer on said gate insulating film; patterning said gate insulating layer with said gate electrode as a mask so that a surface of said semiconductor is exposed at a portion other than that below said gate electrode; introducing impurity ions into said semiconductor layer with said gate electrode as a mask to form source and drain regions; disposing a metal containing film over said semiconductor layer having said gate electrode formed thereon; and removing a portion of said metal containing film located over said gate electrode.
Claim 44
Dependent Claim
88 words
A process for fabricating a transistor comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating film over said gate electrode; forming an amorphous silicon film on said gate insulating film; and adding a catalyst material which accelerates crystallization of said amorphous silicon film and an impurity as a dopant into said amorphous silicon film in alignment with said gate electrode wherein said catalyst material is added to said amorphous silicon film to a concentration not higher than 1×10 20 atoms/cm 3 .
Claim 45
Dependent Claim
88 words
A process for fabricating a transistor comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating film over said gate electrode; forming an amorphous silicon film on said gate insulating film; and adding a catalyst material which accelerates crystallization of said amorphous silicon film and an impurity as a dopant into said amorphous silicon film in alignment with said gate electrode wherein said catalyst material is added to said amorphous silicon film to a concentration not higher than 1×10 20 atoms/cm 3 .
Claim 46
Dependent Claim
67 words
The process of claim 38 comprising the further step of: forming a source region and a drain region and an active area provided between said source region and drain region, wherein said source and drain region contains a catalyst material at a concentration higher than 1×10 17 atoms/cm 3 and said active region contains the catalyst material at a concentration lower than 1×10 17 atoms/cm 3 .
Claim 47
Dependent Claim
86 words
A process for fabricating a transistor comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating film over said gate electrode; forming an amorphous silicon film on said gate insulating film; introducing an impurity as a dopant into said amorphous silicon film in alignment with said gate electrode; and adhering a material containing a catalyst material onto said amorphous silicon film wherein said amorphous silicon film contains said catalyst material in a concentration not higher than 1×10 20 atoms/cm 3 .
Claim 48
Dependent Claim
86 words
A process for fabricating a transistor comprising the steps of: forming a gate electrode on a substrate; forming a gate insulating film over said gate electrode; forming an amorphous silicon film on said gate insulating film; introducing an impurity as a dopant into said amorphous silicon film in alignment with said gate electrode; and adhering a material containing a catalyst material onto said amorphous silicon film wherein said amorphous silicon film contains said catalyst material in a concentration not higher than 1×10 20 atoms/cm 3 .
Claim 49
Dependent Claim
67 words
The process of claim 40 comprising the further step of: forming a source region and a drain region and an active area provided between said source region and drain region, wherein said source and drain region contains a catalyst material at a concentration higher than 1×10 17 atoms/cm 3 and said active region contains the catalyst material at a concentration lower than 1×10 17 atoms/cm 3 .
Claim 50
Independent Claim
113 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of: forming a gate electrode on a glass substrate; forming a gate insulating layer on said gate electrode; forming a semiconductor layer over said gate electrode, said semiconductor layer being insulated from said gate electrode by said gate insulating layer interposed therebetween; forming a mask over said semiconductor layer, wherein said mask is formed in a self-alignment manner with respect to said electrode; introducing impurity ions into said semiconductor layer in a self-alignment manner with respect to said mask to form source and drain regions, and forming a metal silicide layer on said semiconductor layer having said mask formed thereon.
Claim 51
Independent Claim
113 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of: forming a gate electrode on a glass substrate; forming a gate insulating layer on said gate electrode; forming a semiconductor layer over said gate electrode, said semiconductor layer being insulated from said gate electrode by said gate insulating layer interposed therebetween; forming a mask over said semiconductor layer, wherein said mask is formed in a self-alignment manner with respect to said electrode; introducing impurity ions into said semiconductor layer in a self-alignment manner with respect to said mask to form source and drain regions, and forming a metal silicide layer on said semiconductor layer having said mask formed thereon.
Claim 52
Dependent Claim
19 words
The method of claim 42 wherein said mask is formed by exposure from a back of said glass substrate.
Claim 53
Dependent Claim
19 words
The method of claim 42 wherein said metal silicide layer is formed on at least said source and drain.
Claim 54
Dependent Claim
18 words
The method of claim 42 wherein said metal silicide layer is deposited on said semiconductor layer by sputtering.
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