US4965213A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Silicon-on-insulator transistor with body node to source node connection
Assignee: Texas Instruments Inc
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Filing: 1988-07-08
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Granted: 1990-10-23
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Expires: 2008-07-08
Abstract
Abstract A silicon-on-insulator MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact to the body node. A contact region of the same conductivity type as the body node, (for example, a p+ region for an n-channel transistor) is formed within the source region in a self-aligned fashion relative to the gate electrode. Ohmic connection is then made between the abutting source region and the contact region, for example by way of silicidation. Since the contact region is of the same conductivity as the body node, a non-rectifying ohmic contact is made between the source and body nodes of the transistor. For SOI CMOS technology, no additional mask steps are required for formation of the contact, as the source/drain implant masks required for the masking of opposite conductivity type regions can be used for the formation of the contact region.
Inventors
- 👤 Terence G. W. Blake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:39
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6708; H10D30/6711; H10D30/6706; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/40
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
228 words
A method of fabricating an integrated circuit in a semiconductor layer overlying an insulating film, comprising: defining first and second portions of said semiconductor layer, said first and second portions of first and second conductivity types, respectively; forming a gate electrode over each of said first and second portions; applying a first mask layer over said first and second portions to expose a contact region adjacent a source side of the gate electrode over said first portion and to expose source and drain regions adjacent said gate electrode over said second portion, and to cover a contact region adjacent a source side of the gate electrode over said second portion and to cover source and drain regions adjacent the gate electrode over said first portion; doping the exposed locations of said first and second portions with a dopant of said first conductivity type; applying a second mask layer over said first and second portions to expose the contact region of said second portion and the source and drain regions of said first portion, and to cover said contact region of said first portion and the source and drain regions of said second portion; doping the exposed portions of said first and second portions with a dopant of said second conductivity type; and forming a silicide film over the source and contact regions of said first and second portions.
Claim 2
Independent Claim
228 words
A method of fabricating an integrated circuit in a semiconductor layer overlying an insulating film, comprising: defining first and second portions of said semiconductor layer, said first and second portions of first and second conductivity types, respectively; forming a gate electrode over each of said first and second portions; applying a first mask layer over said first and second portions to expose a contact region adjacent a source side of the gate electrode over said first portion and to expose source and drain regions adjacent said gate electrode over said second portion, and to cover a contact region adjacent a source side of the gate electrode over said second portion and to cover source and drain regions adjacent the gate electrode over said first portion; doping the exposed locations of said first and second portions with a dopant of said first conductivity type; applying a second mask layer over said first and second portions to expose the contact region of said second portion and the source and drain regions of said first portion, and to cover said contact region of said first portion and the source and drain regions of said second portion; doping the exposed portions of said first and second portions with a dopant of said second conductivity type; and forming a silicide film over the source and contact regions of said first and second portions.
Claim 3
Dependent Claim
51 words
The method of claim 1, wherein said doping steps comprise: implanting dopant ions of said first conductivity type into the portions exposed by the first mask layer; implanting dopant ions of said second conductivity type into the portions exposed by the second mask layer; and annealing to diffuse the implanted ions.
Claim 4
Dependent Claim
20 words
The method of claim 1, wherein said doping steps dope the doped portions of the semiconductor layer throughout its thickness.
Claim 5
Dependent Claim
177 words
The method of claim 1, further comprising, prior to the step of forming said silicide film: forming sidewall dielectric filaments on the sides of said gate electrodes to cover a portion of the semiconductor layer adjacent to the gate electrodes; applying a third mask layer over said first and second portions to expose the contact region of said first portion and the source and drain regions of said second portion, and to cover said contact region of said second portion and the source and drain regions of said first portion; additionally doping the exposed locations of said first and second portions with a dopant of said first conductivity type; applying a fourth mask layer over said first and second portions to expose the contact region of said second portion and the source and drain regions of said first portion, and to cover said contact region of said first portion and the source and drain regions of said second portion; additionally doping the exposed locations of said first and second portions with a dopant of said second type.
Claim 6
Dependent Claim
20 words
The method of claim 4, wherein said additionally doping doping more highly dope the semiconductor layer than said doping steps.
Claim 7
Dependent Claim
17 words
The method of claim 1, wherein said defining step comprises forming semiconductor mesas on said insulating film.
References Cited (Backward Citations)
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