Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
176 words
A method of fabricating a transistor in a semiconductor layer overlying an insulating film, comprising: defining an active portion of said semiconductor layer of a first conductivity type; forming a gate electrode over said active portion; applying a first mask layer over said active portion to protect a first contact region on a first side of said gate electrode and a second contact region on a second side of said gate electrode; doping regions of said active portion not protected by said first mask layer with dopant of a second conductivity type; applying a second mask layer over said active portion to protect said first and second contact regions, and to protect portions of said doped regions adjacent to said first and second contact regions; forming a silicide film over said doped regions not protected by said second mask layer; forming an interlevel dielectric layer overall; etching a contact via through said interlevel dielectric to contact said first contact region; and forming a metal line in contact with said first contact region through said contact via.
Claim 2
Independent Claim
176 words
A method of fabricating a transistor in a semiconductor layer overlying an insulating film, comprising: defining an active portion of said semiconductor layer of a first conductivity type; forming a gate electrode over said active portion; applying a first mask layer over said active portion to protect a first contact region on a first side of said gate electrode and a second contact region on a second side of said gate electrode; doping regions of said active portion not protected by said first mask layer with dopant of a second conductivity type; applying a second mask layer over said active portion to protect said first and second contact regions, and to protect portions of said doped regions adjacent to said first and second contact regions; forming a silicide film over said doped regions not protected by said second mask layer; forming an interlevel dielectric layer overall; etching a contact via through said interlevel dielectric to contact said first contact region; and forming a metal line in contact with said first contact region through said contact via.
Claim 3
Dependent Claim
25 words
The method of claim 1, wherein said contact via overlaps a boundary between said first contact region and the adjacent portion of said dope region.
Claim 4
Dependent Claim
16 words
The method of claim 1, wherein said contact via is disposed within said first contact region.
Claim 5
Dependent Claim
48 words
The method of claim 1, further comprising: etching a second contact via through said interlevel dielectric layer to contact the doped region on said first side of said gate electrode; and wherein said metal line is formed also in contact with said doped region through second contact via.
Claim 6
Dependent Claim
83 words
The method of claim 1, further comprising, after said step of doping said regions; forming sidewall dielectric filaments on said first and second sides of said gate electrode; applying a third mask layer over said active portion to protect said first and second contact regions additionally doping first and second regions of said active portion not protected by said first mask layer with dopant of a second conductivity type, said additionally doping step resulting in heavier doping concentration than said first doping step.
Claim 7
Independent Claim
237 words
A method of fabricating a transistor in a semiconductor layer overlying an insulating film, comprising: defining an active portion of said semiconductor layer of a first conductivity type; forming a gate electrode over said active portion; applying a first mask layer over said active portion to protect a first contact region on a first side of said gate electrode and a second contact region on a second side of said gate electrode; doping first and second regions of said active portion not protected by said first mask layer with dopant of a second conductivity type, said first and second doped regions disposed on said first and second sides of said gate electrode respectively; applying a second mask layer over said active portion to protect said first and second contact regions, and to protect portions of said first and second doped regions adjacent to said first and second contact regions, respectively; forming a silicide film over said first and second doped regions where not protected by said second mask layer; forming an interlevel dielectric layer overall; selecting either said first or said second doped regions as the source of the transistor; etching a contact via through said interlevel dielectric to contact the selected doped region and to contact the contact region on the side of said selected doped region; forming a metal line in contact with said selected doped region and the contact region through said contact vias.
Claim 8
Independent Claim
237 words
A method of fabricating a transistor in a semiconductor layer overlying an insulating film, comprising: defining an active portion of said semiconductor layer of a first conductivity type; forming a gate electrode over said active portion; applying a first mask layer over said active portion to protect a first contact region on a first side of said gate electrode and a second contact region on a second side of said gate electrode; doping first and second regions of said active portion not protected by said first mask layer with dopant of a second conductivity type, said first and second doped regions disposed on said first and second sides of said gate electrode respectively; applying a second mask layer over said active portion to protect said first and second contact regions, and to protect portions of said first and second doped regions adjacent to said first and second contact regions, respectively; forming a silicide film over said first and second doped regions where not protected by said second mask layer; forming an interlevel dielectric layer overall; selecting either said first or said second doped regions as the source of the transistor; etching a contact via through said interlevel dielectric to contact the selected doped region and to contact the contact region on the side of said selected doped region; forming a metal line in contact with said selected doped region and the contact region through said contact vias.
Claim 9
Dependent Claim
30 words
The method of claim 6, wherein said contact via in contact with the contact region overlaps a boundary between said contact region and the adjacent portion of said doped region.
Claim 10
Dependent Claim
22 words
The method of claim 6, wherein said contact via in contact with the contact region is disposed within said first contact region.
Claim 11
Dependent Claim
84 words
The method of claim 6, further comprising, after said step of doping said regions; forming sidewall dielectric filaments on said first and second sides of said gate electrode; applying a third mask layer over said active portion to protect said first and second contact regions; additionally doping said first and second regions of said active portion not protected by said first mask layer with dopant of a second conductivity type, said additionally doping step resulting in heavier doping concentration than said first doping step.
Claim 12
Dependent Claim
18 words
The method of claim 9, wherein said first and second contact regions are adjacent to said gate electrode.
Claim 13
Dependent Claim
40 words
The method of claim 9, wherein said first and second contact regions are not adjacent said gate electrode; and wherein said third mask layer protects the doped region disposed between said first and second contact regions and said gate electrode.
Claim 14
Dependent Claim
18 words
The method of claim 6, wherein said first and second contact regions are adjacent to said gate electrode.