Shaping ATE bursts, particularly in gallium arsenide

Claim 2

Burst-shaping circuitry which comprises a palette lookup including a plurality of register means, a corresponding plurality of multiplexers, and a pulse modulator, each said register means being selectively settable, and each said register means being arranged to deliver through a corresponding said multiplexer to said pulse modulator data commands into said multiplexer through said register cooperating with its respective multiplexer.

Claim 3

ATE burst circuitry comprising a multiplicity of timing generators, each said timing generator including a count register settable to determine desired number of counts, a match element transmitting an edge upon the reaching of said desired number, a vernier, a palette lookup for receiving data from a memory in successive bit groups and issuing commensurate commands, and a pulse modulator for receiving an edge from said vernier and said command from said palette lookup, said command selectively restricting passage of said edge through said pulse modulator.

Claim 4

ATE burst circuitry comprising a multiplicity of timing generators, each said timing generator including a count register settable to determine desired number of counts, a match element transmitting an edge upon the reaching of said desired number, a vernier, a palette lookup for receiving data from a memory in successive bit groups and issuing commensurate commands, and a pulse modulator for receiving an edge from said vernier and said command from said palette lookup, said command selectively restricting passage of said edge through said pulse modulator.

Claim 5

The circuitry of claim 2 in which said circuitry is implemented in a single chip.

Claim 6

The circuitry of claim 3 in which said chip is of gallium arsenide.

Claim 7

The circuitry of claim 2 which includes also a timing enable register, said timing enable register being selectively settable to enable either high-low drive or driver on-off function in said pulse modulator.

Claim 8

The circuitry of claim 2 in which certain of said timing generators may be selectively placed in a comparator period mode.

Claim 9

The circuitry of claim 6 in which a pair of said timing generators may be placed in a cooperative relation in said comparator mode, said pair being arranged to accept as bits two palette lookup outputs and command using the four choice outputs thus available one of four different comparator strobe treatments.

Claim 10

The circuitry of claim 6 in which at least one of said timing generators has an edge strobe high command capability, and at least another has an edge strobe low capability.

Claim 11

The circuitry of claim 6 in which at least one of said timing generators has an open window strobe capability and at least another one of said timing generators has a close window strobe capability.

Claim 12

The circuitry of claim 7 in which said treatments are "don't care", "expect low", "expect high", and "expect midband".

Claim 15

The method of claim 11 wherein the plurality of period clock signals comprises a first period clock signal and a second period clock signal generated from a single clock signal, the first and second period clock signals being about 180° out of phase.

Claim 16

The method of claim 12 wherein each channel is formed with GaAs semiconductor components.

Claim 17

The method of claim 11 wherein automatic test equipment includes a computer having memory storing a test pattern and each timing generator comprises programmable delay circuitry which delays a timing signal in response to a digital value entered into a register, and a) the step of constructing a calibration table comprises constructing a calibration table in memory associated with the computer; b) the step of adjusting comprises retrieving values stored in the test value representing programmed intervals and adding to them a delay value computed from the values stored in the calibration table; and c) the step of using the adjusted value comprises loading the adjusted value into a register controlling the programmable delay circuitry.

Claim 18

The method of claim 14 wherein the test pattern specifies a burst of test signals and the adjusted values are loaded into the register at the start of the burst and are not changed during the burst.

Claim 19

The method of claim 11 wherein the step of adjusting comprises: a) when the programmed period of the period clock signals matches a value for which values are stored in the calibration table, using a value in the calibration table for adjusting the value of a programmed interval; and b) when the programmed period of the period clock signals does not match a value for which values are stored in the calibration, interpolating between two values stored in the table and using the interpolated value for adjusting the value of a programmed interval.

Claim 20

The method of claim 11 wherein a) the step of constructing a calibration table includes storing in the table corrections for differential delays for each timing generator, the table including entries at a programmed interval for programmed period values; and b) the step of adjusting the value of a programmed interval also includes retrieving from the table one of the values stored in step a) and adjusting the value of the programmed interval based on that value.

Claim 21

Automatic test equipment which generates test signals at a frequency which can be programmed, comprising: a) a computer and a data bus; b) means for generating a test pattern burst, the test pattern comprising a plurality of successive codes for each channel of the automatic test equipment; c) a plurality of channel circuits, each containing: i) a plurality of timing generators which generate timing signals, each having: A) programmable delay circuit having a pulse input, a digital delay input and timing pulse output which occurs an amount of time following the pulse input which is controlled by the digital delay input; B) a timing register having an input connected to the digital data bus and an output connected to the programmable delay circuitry; ii) a pulse modulator circuit having timing signal inputs each coupled to a timing generator in the channel, a data input coupled to the means for generating a test pattern and for providing the successive test codes to the pulse modulator, and timing signal outputs, the pulse modulator gating selected timing signals from its input to its output in accordance with the value at its data input; iii) a drive format circuit responsive to a plurality of timing signal outputs from the pulse modulator, said drive format circuit producing an output signal starting upon the occurrence of any one of a first subset of the timing signal outputs and ending upon the occurrence of any one of a second subset of the timing signal outputs; and d) wherein the computer includes i) means for storing a plurality of calibration tables, at least one of the tables storing calibration values for each timing generator to be used at different programmed frequencies; ii) means for storing a desired delay value for each of the timing generators during a pattern burst, the computer further including means for adjusting the desired delay values based on values in the calibration tables and the programmed frequency; and iii) means for loading the adjusted values into the timing registers.

Claim 22

Automatic test equipment which generates test signals at a frequency which can be programmed, comprising: a) a computer and a data bus; b) means for generating a test pattern burst, the test pattern comprising a plurality of successive codes for each channel of the automatic test equipment; c) a plurality of channel circuits, each containing: i) a plurality of timing generators which generate timing signals, each having: A) programmable delay circuit having a pulse input, a digital delay input and timing pulse output which occurs an amount of time following the pulse input which is controlled by the digital delay input; B) a timing register having an input connected to the digital data bus and an output connected to the programmable delay circuitry; ii) a pulse modulator circuit having timing signal inputs each coupled to a timing generator in the channel, a data input coupled to the means for generating a test pattern and for providing the successive test codes to the pulse modulator, and timing signal outputs, the pulse modulator gating selected timing signals from its input to its output in accordance with the value at its data input; iii) a drive format circuit responsive to a plurality of timing signal outputs from the pulse modulator, said drive format circuit producing an output signal starting upon the occurrence of any one of a first subset of the timing signal outputs and ending upon the occurrence of any one of a second subset of the timing signal outputs; and d) wherein the computer includes i) means for storing a plurality of calibration tables, at least one of the tables storing calibration values for each timing generator to be used at different programmed frequencies; ii) means for storing a desired delay value for each of the timing generators during a pattern burst, the computer further including means for adjusting the desired delay values based on values in the calibration tables and the programmed frequency; and iii) means for loading the adjusted values into the timing registers.

Claim 23

The automatic test equipment of claim 18 additionally comprising in each of the channel circuits a compare format circuit responsive to a plurality of timing signal outputs from the pulse modulator circuit.