Timing generation in an automatic electrical test system

Claim 3

The method of claim 1, wherein the first T1 value comprises a first T1 counter value and a first T1 vernier value, and wherein the first T2 value comprises a first T2 counter value and a first T2 vernier value, and wherein the first period-minus-T1 value comprises a first period-minus-T1 counter value and a first period vernier value.

Claim 4

The method of claim 2, wherein the step of generating a first internal period start comprises the step of generating the first internal period start offset from the first external period start by the first T1 counter value.

Claim 5

The method of claim 2, wherein the step of generating a first internal period start comprises the step of generating a first T1 terminal count according to the first T1 counter value.

Claim 6

The method of claim 4, wherein the step of generating a first T1 marker and a first T2 marker comprises the steps of: delaying the first internal period start according to the first T1 vernier value; generating a first T2 terminal count according to the first T2 counter value; delaying the first T2 terminal count according to the first T2 vernier value.

Claim 7

The method of claim 2, further comprising the steps of: receiving a second set of timing parameters corresponding to a second external period start, the second set of timing parameters comprising a second T1 value, a second T2 value, and a second period-minus-T1 value; generating a second internal period start, the second internal period start offset from the first internal period start by the first period-minus-T1 value plus the second T1 value; generating a second T1 marker and a second T2 marker, the second T1 marker offset from the second internal period start by the second T1 value, the second T2 marker offset from the second internal period start by the second T2 value.

Claim 8

The method of claim 6, wherein the second set of timing parameters are synchronized by the first internal period start.

Claim 9

The method of claim 6, wherein the second T1 value comprises a second T1 counter value and a second T1 vernier value, and wherein the second T2 value comprises a second T2 counter value and a second T2 vernier value, and wherein the second period-minus-T1 value comprises a second period-minus-T1 counter value and a second period vernier value.

Claim 10

The method of claim 8, wherein the step of generating a second internal period start further comprises the steps of: generating an accumulated period vernier value equal to the first period vernier value plus the second period vernier value; determining an accumulated T1 vernier value equal to the second T1 vernier value plus the accumulated period vernier value; determining an accumulated T2 vernier value equal to the second T2 vernier value plus the accumulated period vernier value.

Claim 11

The method of claim 9, wherein the step of generating a second internal period start comprises the step of generating the second internal period start offset from the first internal period start by the first period-minus-T1 counter value plus the second T1 counter valve.

Claim 12

The method of claim 10, wherein the step of generating a second T1 marker and a second T2 marker comprises the steps of: delaying the second internal period start according to the accumulated T1 vernier value; generating a second T2 terminal count according to the second T2 counter value; delaying the second T2 terminal count according to the accumulated T2 vernier value.

Claim 15

The apparatus of claim 12, wherein the first T1 value comprises a first T1 counter value and a first T1 vernier value, and wherein the first T2 value comprises a first T2 counter value and a first T2 vernier value, and wherein the first period-minus-T1 value comprises a first period-minus-T1 counter value and a first period vernier value.

Claim 16

The apparatus of claim 13, wherein the means for generating a first internal period start comprises means for generating the first internal period start offset from the first external period start by the first T1 counter value.

Claim 17

The apparatus of claim 13, wherein the means for generating a first internal period start comprises means for generating a first T1 terminal count according to the first T1 counter value.

Claim 18

The apparatus of claim 15, wherein the means for generating a first T1 marker and a first T2 marker comprises: means for delaying the first internal period start according to the first T1 vernier value: means for generating a first T2 terminal count according to the first T2 counter value; means for delaying the first T2 terminal count according to the first T2 vernier value.

Claim 19

The apparatus of claim 13, further comprising: means for receiving a second set of timing parameters corresponding to a second external period start, the second set of timing parameters comprising a second T1 value, a second T2 value, and a second period-minus-T1 value; means for generating a second internal period start, the second internal period start offset from the first internal period start by the first period-minus-T1 value plus the second T1 value; means for generating a second T1 marker and a second T2 marker, the second T1 marker offset from the second internal period start by the second T1 value, the second T2 marker offset from the second internal period start by the second T2 value.

Claim 20

The apparatus of claim 17, wherein the second set of timing parameters are synchronized by the first internal period start.

Claim 21

The apparatus of claim 17, wherein the second T1 value comprises a second T1 counter value and a second T1 vernier value, and wherein the second T2 value comprises a second T2 counter value and a second T2 vernier value, and wherein the second period-minus-T1 value comprises a second period-minus-T1 counter value and a second period vernier value.

Claim 22

The apparatus of claim 19, wherein the means for generating a second internal period start further comprises: means for generating an accumulated period vernier value equal to the first period vernier value plus the second period vernier value; means for determining an accumulated T1 vernier value equal to the second T1 vernier value plus the accumulated period vernier value; means for determining an accumulated T2 vernier value equal to the second T2 vernier value plus the accumulated period vernier value.

Claim 23

The apparatus of claim 20, wherein the means for generating a second internal period start comprises means for generating the second internal period start offset from the first internal period start by the first period-minus-T1 counter value plus the second T1 counter value.

Claim 24

The apparatus of claim 21, wherein the means for generating a second T1 marker and a second T2 marker comprises: means for delaying the second internal period start according to the accumulated T1 vernier value; means for generating a second T2 terminal count according to the second T2 counter value; means for delaying the second T2 terminal count according to the accumulated T2 vernier value.

Claim 25

A circuit for generating T1 and T2 timing markers in an automatic electrical test system, comprising: first-in-first-out memory means coupled to receive and store a timing parameter address, the timing parameter address synchronized by an external period signal; memory means storing a plurality of timing parameter entries, the memory means coupled to receive the timing parameter address from the first-in-first-out memory means, the timing parameter address synchronized by an internal period signal, the timing parameter address selecting one of the timing parameter entries; adder circuit coupled to receive the timing parameter entries, the adder circuit generating a T1 marker value and a T2 marker value; counter circuit coupled to receive the T1 marker value and the T2 marker value, the counter circuit generating the internal period signal, the T1 marker, and the T2 marker.

Claim 26

A circuit for generating T1 and T2 timing markers in an automatic electrical test system, comprising: first-in-first-out memory means coupled to receive and store a timing parameter address, the timing parameter address synchronized by an external period signal; memory means storing a plurality of timing parameter entries, the memory means coupled to receive the timing parameter address from the first-in-first-out memory means, the timing parameter address synchronized by an internal period signal, the timing parameter address selecting one of the timing parameter entries; adder circuit coupled to receive the timing parameter entries, the adder circuit generating a T1 marker value and a T2 marker value; counter circuit coupled to receive the T1 marker value and the T2 marker value, the counter circuit generating the internal period signal, the T1 marker, and the T2 marker.

Claim 27

The circuit of claim 23, wherein each timing parameter entry comprises a T1 counter value, a T1 vernier value, a T2 counter value, a T2 vernier value, a period-minus-T1 counter value, and a period vernier value.

Claim 28

The circuit of claim 24, wherein the T1 marker value comprises a T1 count and an accumulated T1 vernier value, and wherein the T2 marker value comprises a T2 count and an accumulated T2 vernier value.

Claim 29

The circuit of claim 25, wherein the adder circuit comprises: first adder means coupled to receive the period vernier value, the first adder means generating an accumulated period vernier value by adding the period vernier value and a delayed period vernier value; second adder means coupled to receive the T1 vernier value and the accumulated period vernier value, the second adder means generating the accumulated T1 vernier value by adding the T1 vernier value and the accumulated period vernier value; third adder means coupled to receive the T2 vernier value and the accumulated period vernier value, the third adder means generating the accumulated T2 vernier value by adding the T2 vernier value and the accumulated period vernier value; fourth adder means coupled to receive a delayed period-minus-T1 counter value and the T1 counter value, the fourth adder means coupled to receive a delayed carry out from the first adder means, the fourth adder means generating the T1 count by adding the delayed period-minus-T1 counter value and the T1 counter value and the delayed carry out.

Claim 30

The circuit of claim 26, wherein the counter circuit comprises: first counter means coupled to receive the T1 count and a base period signal, the first counter means counting down from the T1 count synchronized by the base period signal, the first counter means generating the internal period signal when the T1 count expires; second counter means coupled to receive the T2 count and the base period signal, the second counter means counting down from the T2 count synchronized by the base period signal, the second counter means generating a T2 terminal count signal when the T1 count expires; first vernier means coupled to receive the internal period signal and the accumulated T1 vernier value, the first vernier means generating the T1 marker by delaying the internal period signal according to the accumulated T1 vernier value; second vernier means coupled to receive the T2 terminal count signal and the accumulated T2 vernier value, the second vernier means generating the T2 marker by delaying the T2 terminal count signal according to the accumulated T1 vernier value.