Event sequencer for automatic test equipment

Claim 2

A test system for testing an integrated circuit by providing test signals to one or more leads of said integrated circuit, comprising: (a) a global sequencer including a clock signal generator for generating a clock signal, means for generating a time zero signal using said clock signal to indicate the start of a test sequence, and means for generating a period vernier value indicating an offset form said clock signal for the start of each of a plurality of test cycles in said test sequence; and (b) a plurality of local sequencers, each of said local sequencers being coupled to a separate one of said leads of said integrated circuit, each said local sequencer being responsive to said clock signal and said period vernier value for generating an edge in a signal for one of said leads within one of said test cycles defined by said period vernier value in said test sequence, such that said test cycle need not be a multiple of said clock signal.

Claim 3

A test system for testing an electronic circuit having a plurality of leads, comprising: (a) a global sequencer including means for generating a global clock signal; means for generating, using said global clock signal, a global time zero signal indicating the beginning of a test period; means coupled to said means for generating a global clock signal for generating a global strobe time zero signal to establish a time for collecting data at the end of said test period; and (b) a plurality of local sequencer, each local sequencer being coupled to one of said leads, each local sequencer generating, in said test period, a programmable number of signal transitions of a test signal to said lead; said local sequencers being programmable with said number of signal transitions for said plurality of local sequencers such that said local sequencers can have different numbers of transitions in any given test period; and means, in each of said local sequencers, for providing data form said lead in response to said global strobe time zero signal.

Claim 4

A test system for testing an electronic circuit having a plurality of leads, comprising: (a) a global sequencer including means for generating a global clock signal; means for generating, using said global clock signal, a global time zero signal indicating the beginning of a test period; means coupled to said means for generating a global clock signal for generating a global strobe time zero signal to establish a time for collecting data at the end of said test period; and (b) a plurality of local sequencer, each local sequencer being coupled to one of said leads, each local sequencer generating, in said test period, a programmable number of signal transitions of a test signal to said lead; said local sequencers being programmable with said number of signal transitions for said plurality of local sequencers such that said local sequencers can have different numbers of transitions in any given test period; and means, in each of said local sequencers, for providing data form said lead in response to said global strobe time zero signal.

Claim 5

The test system of claim 2 further comprising: second means for generating a second global time zero signal coupled to said local sequencers; and second means for generating a second global strobe time zero signal coupled to said means for providing data; such that separate groups of said local sequencers can receive separate global time zero and global strobe time zero signals to asynchronously and independently test different groups of said leads of said circuit.

Claim 6

A local sequencer for a test system, said test system having a plurality of said local sequencers, each local sequencer being coupled to a lead of a device under test, said local sequencer comprising: memory means for storing the time and type of events applied to and received from said device under test and for storing offsets for said time according to said event type; adder means for adding said time from said memory, one of said offsets and an externally provided global test period offset to provide a calibrated time; means for delaying an external clock signal by said calibrated time to produce a delayed clock signal; and edge generator means, coupled to said means for delaying, for producing a test signal transition for said lead at a time indicated by said delayed clock signal.

Claim 7

A local sequencer for a test system, said test system having a plurality of said local sequencers, each local sequencer being coupled to a lead of a device under test, said local sequencer comprising: memory means for storing the time and type of events applied to and received from said device under test and for storing offsets for said time according to said event type; adder means for adding said time from said memory, one of said offsets and an externally provided global test period offset to provide a calibrated time; means for delaying an external clock signal by said calibrated time to produce a delayed clock signal; and edge generator means, coupled to said means for delaying, for producing a test signal transition for said lead at a time indicated by said delayed clock signal.

Claim 8

The local sequencer of claim 4 wherein said memory means comprises a functional memory for storing event types, a local memory for storing event times and a calibration memory for storing said offsets.

Claim 9

The local sequencer of claim 5 wherein said local memory also stores one of (a) an event type and (b) a reference to said functional memory for a plurality of event times.

Claim 10

The local sequencer of claim 6 further comprising event type decode logic having inputs coupled to said functional memory and said local memory and an output coupled to said calibration memory.

Claim 11

The local sequencer of claim 6 wherein said local memory also stores for each event time a flag indicating whether said event is the last event in a sequence of events.

Claim 12

The local sequencer of claim 5 wherein said event time is defined as the time since a last event.

Claim 13

The local sequencer of claim 4 further comprising a register coupled to the output of said adder for storing said calibrated time, and wherein said means for delaying includes a linear delay circuit having an input coupled to an output of said register.

Claim 14

A sequencer for providing test signals to a circuit being tested, comprising: memory means for storing timing data indicating the time for each of a sequence of signal transitions and functional data indicating the state to be transitioned to for said sequence, wherein a bit of said functional data can apply to a plurality of signal transitions; decoding means, coupled to said memory means, having a first input coupled to receive said timing data and a second input coupled to receive said functional data, for providing an output indicating the state and transition time of event signals; and driver means, coupled to said decoding means, for providing said event signals to said circuit being tested.

Claim 15

A sequencer for providing test signals to a circuit being tested, comprising: memory means for storing timing data indicating the time for each of a sequence of signal transitions and functional data indicating the state to be transitioned to for said sequence, wherein a bit of said functional data can apply to a plurality of signal transitions; decoding means, coupled to said memory means, having a first input coupled to receive said timing data and a second input coupled to receive said functional data, for providing an output indicating the state and transition time of event signals; and driver means, coupled to said decoding means, for providing said event signals to said circuit being tested.

Claim 16

The sequencer of claim 11 wherein said memory means comprises a functional memory for storing functional data, a local memory for storing said timing data and a calibration memory for storing offsets for said timing data according to said functional data.

Claim 17

The sequencer of claim 12 wherein said local memory also stores, for a plurality of event times, one of (a) functional data and (b) a reference to said functional memory.

Claim 18

The sequencer of claim 13 wherein said decoding means comprises event type decode logic having inputs coupled to said functional memory and said local memory and an output coupled to said calibration memory.

Claim 19

The sequencer of claim 13 wherein said local memory also stores for each event time a flag indicating whether said event is in the last event in a sequence of events.

Claim 20

A test system for testing an integrated circuit, comprising: (a) a global sequencer including a clock signal generator for generating a clock signal, means for generating a time zero signal using said clock signal to indicate the start of a test sequence, means for generating a period vernier value indicating an offset from said clock signal for the start of each of a plurality of test cycles in said test sequence; and a plurality of local sequencers, each of said local sequencers being coupled to a separate lead of said integrated circuit, for generating, in a test period calibrated to said clock signal, a programmable number of signal transitions, such that said local sequencers can have different numbers of transitions in any given test period, each local sequencer including edge generator means, responsive to said clock signal and said period vernier value, for generating one of said signal transitions in a signal for said lead within a test cycle defined by said period vernier value, such that said test cycle need not be a multiple of said clock signal.

Claim 21

A test system for testing an integrated circuit, comprising: (a) a global sequencer including a clock signal generator for generating a clock signal, means for generating a time zero signal using said clock signal to indicate the start of a test sequence, means for generating a period vernier value indicating an offset from said clock signal for the start of each of a plurality of test cycles in said test sequence; and a plurality of local sequencers, each of said local sequencers being coupled to a separate lead of said integrated circuit, for generating, in a test period calibrated to said clock signal, a programmable number of signal transitions, such that said local sequencers can have different numbers of transitions in any given test period, each local sequencer including edge generator means, responsive to said clock signal and said period vernier value, for generating one of said signal transitions in a signal for said lead within a test cycle defined by said period vernier value, such that said test cycle need not be a multiple of said clock signal.

Claim 22

A test system for testing an integrated circuit, comprising: a global sequencer including a clock signal generator for generating a clock signal, means for generating a time zero signal using said clock signal to indicate the start of a test sequence, means for generating a period vernier value indicating an offset from said clock signal for the start of each of a plurality of test cycles in said test sequence; and a plurality of local sequencers, each of said local sequencers being coupled to a separate lead of said integrated circuit, each local sequencer including memory means for storing timing data indicating the time for each of a sequence of signal transitions and functional data indicating the state to be transitioned to for said sequence, wherein a bit of said functional data can apply to a plurality of signal transitions, decoding means, having a first input coupled to receive said timing data and a second input coupled to receive said functional data, for providing an output indicating the state and transition time of events, edge generator means, coupled to said decoding means and responsive to said clock signal, said period vernier value and said state and transition time of events, for generating an edge in a signal for said lead within a test cycle defined by said period vernier value, such that said test cycle need not be a multiple of said clock signal, and driver means, coupled to said edge generator means, for providing said edges to said leads of said integrated circuit.

Claim 23

A test system for testing an integrated circuit, comprising: a global sequencer including a clock signal generator for generating a clock signal, means for generating a time zero signal using said clock signal to indicate the start of a test sequence, means for generating a period vernier value indicating an offset from said clock signal for the start of each of a plurality of test cycles in said test sequence; and a plurality of local sequencers, each of said local sequencers being coupled to a separate lead of said integrated circuit, each local sequencer including memory means for storing timing data indicating the time for each of a sequence of signal transitions and functional data indicating the state to be transitioned to for said sequence, wherein a bit of said functional data can apply to a plurality of signal transitions, decoding means, having a first input coupled to receive said timing data and a second input coupled to receive said functional data, for providing an output indicating the state and transition time of events, edge generator means, coupled to said decoding means and responsive to said clock signal, said period vernier value and said state and transition time of events, for generating an edge in a signal for said lead within a test cycle defined by said period vernier value, such that said test cycle need not be a multiple of said clock signal, and driver means, coupled to said edge generator means, for providing said edges to said leads of said integrated circuit.

Claim 24

A test system for testing an integrated circuit, comprising: a global sequencer including a clock signal generator for generating a clock signal, means for generating a time zero signal using said clock signal to indicate the start of a test sequence, means for generating a period vernier value indicating an offset from said clock signal for the start of each of a plurality of test cycles; and a plurality of local sequencers, each of said local sequencers being coupled to a separate lead of said integrated circuit, each local sequencer including memory means for storing timing data indicating the time for each of a sequence of signal transitions and functional data indicating the state to be transitioned to for said sequence, wherein a bit of said functional data can apply to a plurality of signal transitions; decoding means, having a first input coupled to receive said timing data and a second input coupled to receive said functional data, for providing an output indicating the state and transition time of events; edge generator means, coupled to said decoding means and responsive to said clock signal, said period vernier value and said state and transition time of events for generating a programmable number of signal transitions in a signal for said lead within a test cycle defined by said period vernier value, such that said test cycle need not be a multiple of said clock signal and said local sequencers can have different numbers of transitions in any given test period, and driver means, coupled to said edge generator means, for providing said signal transitions to said circuit.

Claim 25

A test system for testing an integrated circuit, comprising: a global sequencer including a clock signal generator for generating a clock signal, means for generating a time zero signal using said clock signal to indicate the start of a test sequence, means for generating a period vernier value indicating an offset from said clock signal for the start of each of a plurality of test cycles; and a plurality of local sequencers, each of said local sequencers being coupled to a separate lead of said integrated circuit, each local sequencer including memory means for storing timing data indicating the time for each of a sequence of signal transitions and functional data indicating the state to be transitioned to for said sequence, wherein a bit of said functional data can apply to a plurality of signal transitions; decoding means, having a first input coupled to receive said timing data and a second input coupled to receive said functional data, for providing an output indicating the state and transition time of events; edge generator means, coupled to said decoding means and responsive to said clock signal, said period vernier value and said state and transition time of events for generating a programmable number of signal transitions in a signal for said lead within a test cycle defined by said period vernier value, such that said test cycle need not be a multiple of said clock signal and said local sequencers can have different numbers of transitions in any given test period, and driver means, coupled to said edge generator means, for providing said signal transitions to said circuit.

Claim 26

A local sequencer for a test system having a plurality of said local sequencers, each local sequencer being coupled to a lead of a device under test, comprising: a functional memory for storing event types; a local memory for storing event times, one of (a) an event type and (b) a reference to said functional memory for every event time, and a flag indicating whether said event is the last event in a sequence of events; a calibration memory for storing offsets for said event times according to said event type; event type decode logic having inputs coupled to said functional memory and said local memory and an output coupled to said calibration memory; adder means for adding said time from said memory, one of said offsets and an externally provided global test period offset to provide a calibrated time; means for delaying an external clock signal by said calibrated time to produce a delayed clock signal; and edge generator means, coupled to said means for delaying, for producing a test signal transition to said lead at a time indicated by said delayed clock signal.

Claim 27

A local sequencer for a test system having a plurality of said local sequencers, each local sequencer being coupled to a lead of a device under test, comprising: a functional memory for storing event types; a local memory for storing event times, one of (a) an event type and (b) a reference to said functional memory for every event time, and a flag indicating whether said event is the last event in a sequence of events; a calibration memory for storing offsets for said event times according to said event type; event type decode logic having inputs coupled to said functional memory and said local memory and an output coupled to said calibration memory; adder means for adding said time from said memory, one of said offsets and an externally provided global test period offset to provide a calibrated time; means for delaying an external clock signal by said calibrated time to produce a delayed clock signal; and edge generator means, coupled to said means for delaying, for producing a test signal transition to said lead at a time indicated by said delayed clock signal.