US4926451A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timing controller for high-speed digital integrated circuit
Assignee: Toshiba Corp
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Filing: 1988-10-19
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Granted: 1990-05-15
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Expires: 2008-10-19
Abstract
Abstract There is disclosed a digital integrated circuit device which has high-speed transistors of a selected type. A timing controller is incorporated in this device and performs timing control for an internal digital circuit. The timing controller includes a series-circuit of two flip-flop circuits serving as a frequency-dividing circuit for frequency-dividing a reference clock signal and generating an internal timing signal, and a switch circuit connected to a signal feedback line of these flip-flop circuits. In a normal mode, the switch circuit supplies the internal timing signal output from the flip-flop circuits to the digital integrated circuit. At a desired timing, the switch circuit performs a switching operation in response to a control signal, electrically disconnects the signal feedback line of the flip-flop circuits, and alternatively supplies an external timing signal externally supplied thereto to the digital integrated circuit.
Inventors
- 👤 Kunio Yoshihara
- 👤 Toshiyuki Terada
- 👤 Chiaki Takubo
- 👤 Nobuo Koide
- 👤 Shoichi Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:53
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/12
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
177 words
A timing controller in a digital integrated circuit, said circuit including a selected type of active elements, said timing controller comprising: a frequency dividing circuit for receiving a reference clock signal and for generating a first timing signal, said first timing signal being received by said digital integrated circuit as an internal timing signal, said frequency dividing circuit having an input and an output; and switch circuit means connected to said output and said input of the said frequency dividing circuit, said switch circuit means further receiving a control signal and a second timing signal as an external timing signal, said switch circuit means being switched between two positions in response to the control signal so that in a first position said switch circuit means connects the output of said frequency dividing circuit to the input of said frequency dividing circuit as a signal feedback line, and in a second position connects the second timing circuit to the input of the frequency dividing circuit so that said frequency dividing circuit is controlled by said second timing signal.
Claim 2
Dependent Claim
177 words
A timing controller in a digital integrated circuit, said circuit including a selected type of active elements, said timing controller comprising: a frequency dividing circuit for receiving a reference clock signal and for generating a first timing signal, said first timing signal being received by said digital integrated circuit as an internal timing signal, said frequency dividing circuit having an input and an output; and switch circuit means connected to said output and said input of the said frequency dividing circuit, said switch circuit means further receiving a control signal and a second timing signal as an external timing signal, said switch circuit means being switched between two positions in response to the control signal so that in a first position said switch circuit means connects the output of said frequency dividing circuit to the input of said frequency dividing circuit as a signal feedback line, and in a second position connects the second timing circuit to the input of the frequency dividing circuit so that said frequency dividing circuit is controlled by said second timing signal.
Claim 3
Dependent Claim
22 words
The timing controller according to claim 1 wherein said frequency dividing circuit comprises a series connection of first and second flip-flop circuits.
Claim 4
Dependent Claim
26 words
The timing controller according to claim 2, wherein said second timing circuit has a square wave form and is in synchronism with said reference clock signal.
Claim 5
Dependent Claim
23 words
The timing controller according to claim 3 wherein said switch circuit means comprises a gate circuit having active elements of said selected type.
Claim 6
Dependent Claim
17 words
The timing controller according to claim 4 wherein said active elements are gallium arsenide field effect transistors.
Claim 7
Dependent Claim
31 words
The timing controller according to claim 4, wherein said gate circuit controls the connection of an output signal from the second flip-flop circuit to the input of the first flip-flop circuit.
Claim 8
Dependent Claim
168 words
A high-speed digital integrated circuit device comprising: an integrated circuit including gallium arsenide transistors operating at a gigahertz rate; a frequency dividing circuit receiving a reference clock signal and frequency dividing said reference clock signal to produce a first timing signal which is supplied to said integrated circuit as an internal timing signal, said frequency dividing circuit including first and second cascaded flip-flops; and switch circuit means including gallium arsenide transistors connected to the output of said second flip-flop and the input of said first flip-flop in a signal feedback line, said switch circuit means receiving a control signal and a second timing signal which is externally supplied, said switch circuit means being switched between two positions in response to the control signal so that in first position said switch circuit means connects the output of said second flip-flop to the input of the first flip-flop so as a feedback line, and in a second position connects the input of said first flip-flop with the second timing signal.
Claim 9
Dependent Claim
168 words
A high-speed digital integrated circuit device comprising: an integrated circuit including gallium arsenide transistors operating at a gigahertz rate; a frequency dividing circuit receiving a reference clock signal and frequency dividing said reference clock signal to produce a first timing signal which is supplied to said integrated circuit as an internal timing signal, said frequency dividing circuit including first and second cascaded flip-flops; and switch circuit means including gallium arsenide transistors connected to the output of said second flip-flop and the input of said first flip-flop in a signal feedback line, said switch circuit means receiving a control signal and a second timing signal which is externally supplied, said switch circuit means being switched between two positions in response to the control signal so that in first position said switch circuit means connects the output of said second flip-flop to the input of the first flip-flop so as a feedback line, and in a second position connects the input of said first flip-flop with the second timing signal.
Claim 10
Dependent Claim
36 words
The device according to claim 7, further comprising invertor means connected to said switch circuit means for receiving said external timing signal to produce an inverted timing signal which is applied to said switch circuit means.
Claim 11
Dependent Claim
14 words
The device according to claim 7, wherein said digital integrated circuit includes a multiplexer.
Claim 12
Dependent Claim
14 words
The device according to claim 7, wherein said digital integrated circuit includes a demultiplexer.
Claim 13
Dependent Claim
15 words
The device according to claim 7, wherein said transistors include Schottky gate field effect transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-14 | 1993-11-13 | 1994-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-14 | 1997-11-13 | 1998-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-14 | 2001-11-13 | 2002-05-15 | $7700.00 | Window Closed / Lapsed |