US4031476A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-integer frequency divider having controllable error
Assignee: RCA Corp
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Filing: 1976-05-12
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Granted: 1977-06-21
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Expires: 1996-05-12
Abstract
Abstract System and method for dividing an input frequency to produce an output frequency related to the input frequency by a non-integral ratio. The divider ratio is alternated between the integer values bracketing the non-integer ratio according to the accumulated value of known errors associated with each integer divisor value by comparing the accumulated error value to a given value.
Inventors
- 👤 Edwin Allen Goldberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:52
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/02; H03K21/026; H03K23/00; H03K23/64; H03K23/66; H03K23/662; H03K23/667
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
125 words
A circuit, producing from a signal at a first frequency a signal at a second frequency, said first and second frequencies being related by a non-integral ratio, comprising the combination of: gating means receptive of said first frequency signal for producing pulses in response thereto when enabled by an enabling signal; divider means responsive to said pulses for producing said second frequency signal; and control means responsive to said second frequency signal for enabling said gating means said control means comprising: means for accumulating a known error value associated with said second frequency signal; and means responsive to said means for accumulating for producing said enabling signal and supplying it to said gating means while the accumulated error value is less than a predetermined value.
Claim 2
Dependent Claim
125 words
A circuit, producing from a signal at a first frequency a signal at a second frequency, said first and second frequencies being related by a non-integral ratio, comprising the combination of: gating means receptive of said first frequency signal for producing pulses in response thereto when enabled by an enabling signal; divider means responsive to said pulses for producing said second frequency signal; and control means responsive to said second frequency signal for enabling said gating means said control means comprising: means for accumulating a known error value associated with said second frequency signal; and means responsive to said means for accumulating for producing said enabling signal and supplying it to said gating means while the accumulated error value is less than a predetermined value.
Claim 3
Dependent Claim
38 words
The invention claimed in claim 1 wherein said gating means includes means responsive to the absence of said enabling signal for inhibiting said pulses for one period of said first frequency during one period of said second frequency.
Claim 4
Dependent Claim
172 words
The invention claimed in claim 2 wherein said control means further comprises register means for storing a predetermined error value; comparator means responsive to said means for accumulating and to said register means for producing an output signal of one value when said accumulated error value exceeds said predetermined error value and of another value when dsia accumulated error value does not exceed said predetermined error value; first storage means for storing a first error value related to the divider means division ratio; second storage means for storing a second error value related to the divider means division ratio plus one; and means responsive to said signal at said second frequency for supplying the error value stored in said first storage means to said means for accumulating in response to said one value of the output signal from said comparator means and for supplying the error value stored in said second storage means to said means for accumulating in response to said other value of the output signal from said comparator means.
Claim 5
Independent Claim
102 words
The method of dividing a first frequency signal by a non-integer divisor to produce a second frequency signal comprising the steps of: producing a train of pulses by gating said first frequency signal; dividing said pulse train by an integer value; and inhibiting the production of said pulse train when said second frequency signal includes an error exceeding a desired value wherein said inhibiting step comprises accumulating a known error for each period of said second frequency; comparing said accumulated error to a predetermined value; and producing an inhibiting signal when said comparing step indicates the accumulated error exceeds the predetermined value.
Claim 6
Independent Claim
102 words
The method of dividing a first frequency signal by a non-integer divisor to produce a second frequency signal comprising the steps of: producing a train of pulses by gating said first frequency signal; dividing said pulse train by an integer value; and inhibiting the production of said pulse train when said second frequency signal includes an error exceeding a desired value wherein said inhibiting step comprises accumulating a known error for each period of said second frequency; comparing said accumulated error to a predetermined value; and producing an inhibiting signal when said comparing step indicates the accumulated error exceeds the predetermined value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-06-20 | 1980-12-20 | 1981-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-06-20 | 1984-12-20 | 1985-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-06-20 | 1988-12-20 | 1989-06-21 | $7700.00 | Window Closed / Lapsed |