Patent US5576222A successfully refreshed from Google Patents.
US5576222A
Expired / Lapsed
US
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Method of making a semiconductor image sensor device
Assignee: Semiconductor Energy Laboratory Co Ltd
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Filing: 1994-10-18
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Granted: 1996-11-19
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Expires: 2014-10-18
Abstract
Abstract An image sensor (10) has a substrate (1), an active layer (3') having a source region and a drain region placed on said substrate (1), a gate insulation layer (4') placed on said active layer, and a gate electrode layer (5') on said gate insulation layer (4'). The active layer (3') is produced by the steps of producing amorphous silicon layer by using disilane gas (Si2H6) through Low Pressure CVD process, and annealing said layer at 500 DEG -650 DEG C. for 4-50 hours in nitrogen gas atmosphere. The gate insulation layer (4') is produced through oxidation of the surface of the active layer at high temperature around 900 DEG -1100 DEG C. The oxidation process at high temperature improves the anneal process and improves the active layer. Thus, an image sensor with uniform characteristics is obtained with improved producing yield rate.
Inventors
- 👤 Michio Arai
- 👤 Masaaki Ikeda
- 👤 Kazushi Sugiura
- 👤 Nobuo Furukawa
- 👤 Mitsufumi Kodama
- 👤 Yukio Yamauchi
- 👤 Naoya Sakamoto
- 👤 Takeshi Fukada
- 👤 Masaaki Hiroki
- 👤 Ichirou Takayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:19
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/011; H10F39/016; H10F71/00; H10F71/10; Y; Y02; Y02E; Y02E10/00; Y02E10/50
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
287 words
A method for producing a non single crystal semiconductor device comprising the steps of; placing an amorphous silicon layer on a substrate through low pressure CVD process using disilane gas, effecting solid phase growth to said amorphous silicon layer to obtain an active layer by heating said substrate together with said layer at temperature in the range 500° C.-650° C. for 4-50 hours, producing an insulation layer on said solid phase growth layer by oxidizing the surface of said solid phase growth layer at a temperature in the range 900° C.-1100° C. in an atmosphere selected from dry atmosphere and wet atmosphere, implanting donor impurities into said solid phase growth layer around said insulation layer to form a source and a drain of a transistor, and placing a conductive layer on said insulation layer as a gate electrode, and further comprising depositing a capacitor, a resistor and a switching transistor on said substrate, including the steps of; depositing a resistor layer together with a conductive wiring layer coupled with said resistor layer, said resistor layer being provided at the same time as said conductive layer on said insulation layer as a gate electrode. depositing a capacitor having a dielectric layer sandwiched by a pair of conductive layers, said dielectric layer being provided at the same time as said insulation layer, and said pair of conductive layers being provided at the same time as said active layer and said conductive layer on said insulation layer as a gate electrode, and depositing at least one transistor of MOS structure having an active layer, a gate insulation layer, and a gate electrode, said deposition of said transistor being performed at the same time as said non single crystal semiconductor device.
Claim 2
Independent Claim
287 words
A method for producing a non single crystal semiconductor device comprising the steps of; placing an amorphous silicon layer on a substrate through low pressure CVD process using disilane gas, effecting solid phase growth to said amorphous silicon layer to obtain an active layer by heating said substrate together with said layer at temperature in the range 500° C.-650° C. for 4-50 hours, producing an insulation layer on said solid phase growth layer by oxidizing the surface of said solid phase growth layer at a temperature in the range 900° C.-1100° C. in an atmosphere selected from dry atmosphere and wet atmosphere, implanting donor impurities into said solid phase growth layer around said insulation layer to form a source and a drain of a transistor, and placing a conductive layer on said insulation layer as a gate electrode, and further comprising depositing a capacitor, a resistor and a switching transistor on said substrate, including the steps of; depositing a resistor layer together with a conductive wiring layer coupled with said resistor layer, said resistor layer being provided at the same time as said conductive layer on said insulation layer as a gate electrode. depositing a capacitor having a dielectric layer sandwiched by a pair of conductive layers, said dielectric layer being provided at the same time as said insulation layer, and said pair of conductive layers being provided at the same time as said active layer and said conductive layer on said insulation layer as a gate electrode, and depositing at least one transistor of MOS structure having an active layer, a gate insulation layer, and a gate electrode, said deposition of said transistor being performed at the same time as said non single crystal semiconductor device.
Claim 3
Dependent Claim
24 words
A method according to claim 1, wherein growth rate of said amorphous silicon layer is in the range between 50 Å/minute and 500 Å/minute.
Claim 4
Dependent Claim
24 words
The method as defined by claim 1, wherein said solid phase growth of said amorphous layer is performed by heating in a nitrogen atmosphere.
Claim 5
Dependent Claim
32 words
A method for producing a non single crystal semiconductor device according to claim 1, further comprising the step of performing a hydrogenation on at least said silicon layer in a hydrogen atmosphere.
Claim 6
Dependent Claim
19 words
A method according to claim 4, wherein said hydrogenation is carried out at 400° C. for about 30 minutes.
Claim 7
Dependent Claim
32 words
A method for producing a non single crystal semiconductor device according to claim 2, further comprising the step of performing a hydrogenation on at least said silicon layer in a hydrogen atmosphere.
Claim 8
Dependent Claim
20 words
A method according to claim 6, wherein said hydrogenation is carried out at about 400° C. for about 30 minutes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-19 | 2000-05-20 | 2000-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-19 | 2004-05-20 | 2004-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-19 | 2008-05-20 | 2008-11-19 | $7700.00 | Window Closed / Lapsed |