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US5298455A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for producing a non-single crystal semiconductor device

Assignee: Semiconductor Energy Laboratory Co Ltd
•
Filing: 1992-01-27
•
Granted: 1994-03-29
•
Expires: 2012-01-27
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Abstract

Abstract A MOS-FET transistor is produced on a substrate made of glass which has a non single crystal semiconductor film (2'). The average diameter of a crystal grain in said film is in the range between 0.5 times and 4 times of thickness of said film, and said average diameter is 250 (Aangstroem)-8000 (Aangstroem) , and said film thickness is 500 (Aangstroem)-2000 (Aangstroem). The density of oxygen in the semiconductor film (2') is less than 2*1019/cm3. A photo sensor having PIN structure is also produced on the substrate, to provide an image sensor for a facsimile transmitter together with the transistors. Said film (2') is produced by placing amorphous silicon film on the glass substrate through CVD process using disilane gas, and effecting solid phase growth to said amorphous silicon film by heating the substrate together with said film in nitrogen gas atmosphere. The film (2') thus produced is subject to implantation of dopant for providing a transistor. The film thus produced has high mobility which provides high speed operation of a transistor, and low threshold voltage of a transistor.

Inventors

  • 👤 Michio Arai
  • 👤 Masaaki Ikeda
  • 👤 Kazushi Sugiura
  • 👤 Nobuo Furukawa
  • 👤 Mitsufumi Kodama
  • 👤 Yukio Yamauchi
  • 👤 Naoya Sakamoto
  • 👤 Takeshi Fukada
  • 👤 Masaaki Hiroki
  • 👤 Ichirou Takayama

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 03:05
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/38; H10P14/3802; H04; H04N; H04N1/00; H04N1/024; H04N1/028; H04N1/03; H04N1/031; H04N1/0313; H04N1/0315; H04N1/0316; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10F; H10F30/00; H10F30/20; H10F30/21; H10F30/22; H10F30/223; H10F30/2235; H10P14/24; H10P14/29; H10P14/2901; H10P14/2922; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; Y; Y10; Y10S; Y10S257/00; Y10S257/905

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 144 words
A method for producing a non single crystal semiconductor device comprising the steps of; placing amorphous silicon film on a glass substrate through low pressure CVD process using disilane gas, effecting solid phase growth to said amorphous silicon film by heating said substrate together with said film in nitrogen gas atmosphere to obtain a film having a thickness in the range 500 Å to 200 Å, and crystal grains in said silicon film having an average diameter int he range 250 Å to 8000 Å, and an oxygen density in said film of less than 2×10 19 /cm 3 , producing an insulation film on said solid phase growth film, implanting donor into said solid phase growth film around said insulation film for a source and a drain of a transistor, and placing a conductive film on said insulation film as a gate electrode.
Claim 2
Independent Claim 144 words
A method for producing a non single crystal semiconductor device comprising the steps of; placing amorphous silicon film on a glass substrate through low pressure CVD process using disilane gas, effecting solid phase growth to said amorphous silicon film by heating said substrate together with said film in nitrogen gas atmosphere to obtain a film having a thickness in the range 500 Å to 200 Å, and crystal grains in said silicon film having an average diameter int he range 250 Å to 8000 Å, and an oxygen density in said film of less than 2×10 19 /cm 3 , producing an insulation film on said solid phase growth film, implanting donor into said solid phase growth film around said insulation film for a source and a drain of a transistor, and placing a conductive film on said insulation film as a gate electrode.
Claim 3
Dependent Claim 41 words
A method according to claim 1, wherein temperature for said solid phase growth is in the range between 550° C. and 600° C., and the duration for that solid phase growth is in the range between 8 hours and 56 hours.
Claim 4
Dependent Claim 24 words
A method according to claim 1, wherein growth rate of said amorphous silicon film is in the range between 50 Å/minute and 500 Å/minute.
Claim 5
Dependent Claim 104 words
A method according to claim 1, further comprising the step of depositing a photo sensor which has PIN structure including the steps of; depositing a first conductive film which has a window for a light path on said substrate adjacent to a transistor area, depositing amorphous silicon film which has PIN structure selectively on said first conductive film, depositing second conductive transparent film on said amorphous silicon film, so that a photo-sensor is obtained by said first conductive film, said amorphous silicon film which has PIN structure, and said second conductive film, and effecting wirings between said photo-sensor and said transistors and external circuitry.

References Cited (Backward Citations)

US4363828A Cited
JPS6193663A Cited
US4693759A Cited
US4814292A Cited
EP0310702A1 Cited
EP0383230A2 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-03-28 1997-09-27 1998-03-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-03-28 2001-09-27 2002-03-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-03-28 2005-09-27 2006-03-29 $7700.00 Window Closed / Lapsed

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