US5574928A
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US
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Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments
Assignee: GlobalFoundries Inc
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Filing: 1994-04-26
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Granted: 1996-11-12
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Expires: 2014-04-26
Abstract
Abstract A processor core for supporting the concurrent execution of mixed integer and floating point operations includes integer functional units (110) utilizing 32-bit operand data and a floating point functional unit (22) utilizing up to 82-bit operand data. Eight operand busses (30, 31) connect to the functional units to furnish operand data, and five result busses (32) are connected to the functional units to return results. The width of the operand busses is 41 bits, which is sufficient to communicate either integer or floating point data. This is done using an instruction decoder (18) to apportion a floating point operation which operates on 82-bit floating point operand data into multiple suboperations each associated with a 41-bit suboperand. The operand busses and result busses have an expanded data-handling dimension from the standard integer data width of 32 bits to 41 bits for handling the floating point operands. The floating point functional unit recombines the suboperand data into 82-bits for execution of the floating point operation, and partitions the 82-bit result for output to the result busses. In addition, the excess capacity of the result busses during integer transfers is used to communicate integer flags.
Inventors
- 👤 Scott A. White
- 👤 Michael D. Goddard
- 👤 William M. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 11:46
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F9/30025; G06F9/30036; G06F9/30094; G06F9/30145; G06F9/30149; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3806; G06F9/3814; G06F9/3818; G06F9/382; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3842; G06F9/3854; G06F9/3856; G06F9/3858; G06F9/3885
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
299 words
A processor core for executing operations utilizing operand data and being of integer and floating point types, the processor core comprising: a plurality of n 1 -bit operand busses and an n 1 -bit result bus, n 1 being a positive integer number; an integer functional unit coupled to the operand busses through a plurality of n 2 -bit inputs and coupled to the result bus through an n 2 -bit output, n 2 being a positive integer number less than or equal to n 1 ; and a floating point functional unit coupled to the n 1 -bit operand busses through a plurality of n 1 -bit inputs, and coupled to the result bus through an n 1 -bit output, the floating point functional unit comprising: means for combining a plurality of n 1 -bit operands from the floating point functional unit inputs into n 3 -bit operand data; means for executing a floating point operation utilizing the n 3 -bit operand data; means for generating an n 3 -bit result; means for segmenting the n 3 -bit result into a plurality of n 1 -bit partial results; and means for sending the partial results to the floating point functional unit outputs, the number of bits n 3 being greater than the number of bits n 1 ; an n 1 -bit writeback bus; a reorder buffer for storing results of speculatively executed operations having outputs coupled to the n 1 -bit operand busses and to the n 1 -bit writeback bus and an input coupled to the result bus; and a register file for storing results of speculatively executed operations when the results are no longer speculative having outputs coupled to the n 1 -bit operand busses and input coupled to the n 1 -bit writeback bus.
Claim 2
Dependent Claim
299 words
A processor core for executing operations utilizing operand data and being of integer and floating point types, the processor core comprising: a plurality of n 1 -bit operand busses and an n 1 -bit result bus, n 1 being a positive integer number; an integer functional unit coupled to the operand busses through a plurality of n 2 -bit inputs and coupled to the result bus through an n 2 -bit output, n 2 being a positive integer number less than or equal to n 1 ; and a floating point functional unit coupled to the n 1 -bit operand busses through a plurality of n 1 -bit inputs, and coupled to the result bus through an n 1 -bit output, the floating point functional unit comprising: means for combining a plurality of n 1 -bit operands from the floating point functional unit inputs into n 3 -bit operand data; means for executing a floating point operation utilizing the n 3 -bit operand data; means for generating an n 3 -bit result; means for segmenting the n 3 -bit result into a plurality of n 1 -bit partial results; and means for sending the partial results to the floating point functional unit outputs, the number of bits n 3 being greater than the number of bits n 1 ; an n 1 -bit writeback bus; a reorder buffer for storing results of speculatively executed operations having outputs coupled to the n 1 -bit operand busses and to the n 1 -bit writeback bus and an input coupled to the result bus; and a register file for storing results of speculatively executed operations when the results are no longer speculative having outputs coupled to the n 1 -bit operand busses and input coupled to the n 1 -bit writeback bus.
Claim 3
Dependent Claim
121 words
A processor core as in claim 1, wherein: the processor core is disposed in a generally planar arrangement of substantially rectangular segments each segment extending in a first dimension and the segments being sequentially stacked in a second dimension, wherein the operand, result and writeback busses extend in the second dimension across a plurality of the segments; the register file being ordered in a first segment at one end of the planar arrangement; the reorder buffer being ordered in a second segment adjacent to the first segment; a plurality of integer functional units being ordered in a third segment adjacent to the second segment; and the floating point functional unit being ordered in a fourth segment adjacent to the third segment.
Claim 4
Dependent Claim
122 words
A processor as in claim 2, wherein: the operand busses extend in the second dimension substantially across the register file, completely across the reorder buffer and the integer functional units and partially across the floating point functional unit; the result bus extends in the second dimension substantially across the reorder buffer, completely across the integer functional units and partially across the floating point functional unit so that the number of operand and result bus data lines that extend across a functional unit but do not couple to the functional unit and the length of operand and result bus data lines are reduced; and the writeback bus extends in the second dimension substantially across the reorder buffer and substantially across the register file.
Claim 5
Dependent Claim
36 words
A processor as in claim 1, wherein the number of integer bits n 2 is 32, the number of floating point bits n 3 is 80-or-more and the number of bussed bits n 1 is 40-or-more.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-12 | 2000-05-13 | 2000-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-12 | 2004-05-13 | 2004-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-12 | 2008-05-13 | 2008-11-12 | $7700.00 | Window Closed / Lapsed |