US5157780A
Expired / Lapsed
US
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Master-slave checking system
Assignee: Advanced Micro Devices Inc
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Filing: 1990-06-12
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Granted: 1992-10-20
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Expires: 2010-06-12
Abstract
Abstract The system comprises a pair of error checking processors connected in a master/slave configuration such that the slave receives inputs and outputs of the master, mimics operation of the master based on the inputs to produce mimicked outputs, compares the mimicked outputs with the master outputs and indicates an error condition if the mimicked outputs do not equal the master outputs. A checking circuit forces a difference between the mimicked output and the master output and determines if the master slave configuration accurately determines the presence of the forced error.
Inventors
- 👤 Brett B. Stewart
- 👤 David B. Witt
- 👤 Bo A. Molander
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 03:12
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1629; G06F11/1637; G06F11/22; G06F11/2205; G06F11/2215
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
145 words
A system, comprising: a pair of error checking processors connected in a master/slave configuration such that the slave receives inputs and outputs of the master, mimics operation of the master based on said inputs to produce mimicked outputs, compares said mimicked outputs with said master outputs and indicates an error condition if said mimicked outputs do not equal said master outputs; and checking means for forcing a difference between a mimicked output and a master output to check the operation of said processors, wherein said checking means comprises: input means for receiving data input to said master and passing said data to an input of said slave; data alteration means for selectively altering said data before passing it to said slave so that the data input to said master and slave differ; and means for outputting said receiving data as said outputs of said master.
Claim 2
Independent Claim
145 words
A system, comprising: a pair of error checking processors connected in a master/slave configuration such that the slave receives inputs and outputs of the master, mimics operation of the master based on said inputs to produce mimicked outputs, compares said mimicked outputs with said master outputs and indicates an error condition if said mimicked outputs do not equal said master outputs; and checking means for forcing a difference between a mimicked output and a master output to check the operation of said processors, wherein said checking means comprises: input means for receiving data input to said master and passing said data to an input of said slave; data alteration means for selectively altering said data before passing it to said slave so that the data input to said master and slave differ; and means for outputting said receiving data as said outputs of said master.
Claim 3
Dependent Claim
18 words
A system as claimed in claim 1 wherein said data alteration means alters one bit of said data.
Claim 4
Dependent Claim
16 words
A system as claimed in claim 2 wherein said one bit is a least significant bit.
Claim 5
Dependent Claim
19 words
A system as claimed in claim 1 wherein said checking means comprises a circuit for monitoring said error condition.
Claim 6
Dependent Claim
36 words
A system as claimed in claim 1 wherein said checking means comprises a circuit having a control field register, an address field register and a data field register to store expected outputs of said master processor.
Claim 7
Dependent Claim
35 words
A system as claimed in claim 5 wherein said circuit includes comparators for comparing contents of said control field, address field and data field registers with outputs of said master processor and indicating a match.
Claim 8
Dependent Claim
46 words
A system as claimed in claim 6 wherein said circuit includes means responsive to said comparators indicating a match for sensing a state of a master slave error output of said slave processor and indicating proper operation if said master slave error output indicates an error.
Claim 9
Dependent Claim
38 words
A system as claimed in claim 5 including means for selectively causing said difference between a master output and a mimicked output to appear on a control field output, an address field output and a data field output.
Claim 10
Dependent Claim
52 words
A system as claimed in claim 8 wherein said data alteration means alters one bit and including means for shifting the position of said one bit to selectively cause said difference to appear one bit at a time in said control field output, said address field output and said data field output.
Claim 11
Independent Claim
110 words
A method, comprising: operating a pair of error checking processors in a master/slave configuration such that the slave receives inputs and outputs of the master, mimics operation of the master based on said inputs to produce mimicked outputs, compares said mimicked outputs with said master outputs and indicates an error condition if said mimicked outputs do not equal said master outputs; receiving data input to said master; selectively altering said data before passing it to an input of said slave so that the data input to said master and slave differ; and outputting said received data as said outputs of said master so as to check operation of said processors.
Claim 12
Independent Claim
110 words
A method, comprising: operating a pair of error checking processors in a master/slave configuration such that the slave receives inputs and outputs of the master, mimics operation of the master based on said inputs to produce mimicked outputs, compares said mimicked outputs with said master outputs and indicates an error condition if said mimicked outputs do not equal said master outputs; receiving data input to said master; selectively altering said data before passing it to an input of said slave so that the data input to said master and slave differ; and outputting said received data as said outputs of said master so as to check operation of said processors.
Claim 13
Dependent Claim
19 words
A method as claimed in claim 10 wherein said step of altering comprises altering one bit of said data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-20 | 1996-04-20 | 1996-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-20 | 2000-04-20 | 2000-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-20 | 2004-04-20 | 2004-10-20 | $7700.00 | Window Closed / Lapsed |