Emulator system utilizing a program counter and a latch coupled to an emulator memory for reducing fletch line of instructions stored in the emulator memory

Claim 1

An emulator for a single-chip microcomputer comprising: an emulation memory storing a program to be evaluated and coupled to an address bus for receiving an address and to a data bus for at least outputting a readout instruction; a counter coupled between an address/data bus and the address bus so as to be preset with an address on the address/data bus and to be incremented so as to sequentially output an address to the emulation memory; a latch coupled between the address/data bus and the address bus to latch an address on the address/data bus so as to output the latched address to the emulation memory; a buffer coupled to the address/data bus and the data bus for temporarily storing data which is read out from or written into the emulation memory; and an evaluation chip coupled to the address/data bus for receiving the program to be evaluated through the buffer from the emulation memory, said evaluation chip generating a program fetch signal to the buffer to enable the buffer so as to fetch the instruction to be executed from the emulation memory through the buffer and the address/data bus, the evaluation chip also generating a program preset signal to the counter to cause the counter to be preset with an address on the address/data bus so that the counter is thereafter incremented to supply the address to the emulation memory, whereby the emulation memory is sequentially read out so as to allow a sequential operation, the evaluation chip further generating an address latch signal to the latch to cause the latch to latch an address on the address/data bus so as to supply the latched address to the emulation memory for a branch operation.