US4486827A
Expired / Lapsed
US
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Microprocessor apparatus
Assignee: Zilog Inc
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Filing: 1982-01-18
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Granted: 1984-12-04
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Expires: 2002-01-18
Abstract
Abstract A special reset function is provided in the CPU, using the same control input to the CPU as the normal reset, to reset only the program counter to facilitate the use of a single CPU in a microprocessor development system.
Inventors
- 👤 Masatoshi Shima
- 👤 Federico Faggin
- 👤 Ralph K. Ungermann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:47
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7864
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
191 words
In a microprocessor product development system having a central processing unit and memory connected to a common bus, apparatus for using said central processor unit in both a user mode and a monitor mode while saving the user mode system state when switching to the monitor mode, comprising: said central processor unit including address bus terminals connected to said common bus a plurality of digital logic device means, a first program counter means for storing the program address of a location of said memory, and means responsive to a clock signal for connecting the value of said program counter to said address bus terminals, and said central processor unit means further including means for resetting said first program counter means and said plurality of digital logic device means in response to a reset signal and for resetting only said first program counter means in response to a special reset signal having a different detectable characteristic from said reset signal, whereby the user mode system state is saved when said special reset signal is applied to the central processor unit to switch the system from the user mode to the monitor mode.
Claim 2
Dependent Claim
191 words
In a microprocessor product development system having a central processing unit and memory connected to a common bus, apparatus for using said central processor unit in both a user mode and a monitor mode while saving the user mode system state when switching to the monitor mode, comprising: said central processor unit including address bus terminals connected to said common bus a plurality of digital logic device means, a first program counter means for storing the program address of a location of said memory, and means responsive to a clock signal for connecting the value of said program counter to said address bus terminals, and said central processor unit means further including means for resetting said first program counter means and said plurality of digital logic device means in response to a reset signal and for resetting only said first program counter means in response to a special reset signal having a different detectable characteristic from said reset signal, whereby the user mode system state is saved when said special reset signal is applied to the central processor unit to switch the system from the user mode to the monitor mode.
Claim 3
Dependent Claim
24 words
The combination of claim 1 further comprising second program counter means, and means for tracking said second counter means to said first counter means.
Claim 4
Dependent Claim
24 words
The combination of claim 2 further comprising means for inserting the contents of said second program counter means into said first program counter means.
Claim 5
Dependent Claim
51 words
The combination of claim 1 further comprising memory means for storing a monitor mode program and a user mode program, and means for addressing said monitor mode program when said system is in the monitor mode and for addressing said user mode program when said system is in the user mode.
Claim 6
Dependent Claim
31 words
The combination of claim 1 wherein said central processor unit additionally comprises a single pin through which said reset and said special reset signals are communicated to the central processing unit.
Claim 7
Dependent Claim
145 words
For a microprocessor system having a central processing unit in a single package with connecting pins and a memory that are both connected to a common bus as part of the system, said central processing unit comprising: timing logic, an interrupt enable device, at least one register, a program counter that stores the program address of a location of said memory, means responsive to a first reset signal at a given one of said pins for resetting all of said first program counter, said at least one register, and said timing logic, and for disabling the interrupt enable device, and means responsive to a second reset signal having a characteristic distingishable from said first reset signal at said given pin for resetting said first program counter without resetting either of said at least one register or said timing logic, and without disabling said interrupt device.
Claim 8
Dependent Claim
145 words
For a microprocessor system having a central processing unit in a single package with connecting pins and a memory that are both connected to a common bus as part of the system, said central processing unit comprising: timing logic, an interrupt enable device, at least one register, a program counter that stores the program address of a location of said memory, means responsive to a first reset signal at a given one of said pins for resetting all of said first program counter, said at least one register, and said timing logic, and for disabling the interrupt enable device, and means responsive to a second reset signal having a characteristic distingishable from said first reset signal at said given pin for resetting said first program counter without resetting either of said at least one register or said timing logic, and without disabling said interrupt device.
Claim 9
Dependent Claim
34 words
The central processing unit of claim 6 which additionally comprises means connected to said given pin for discriminating between said first and second reset signals applied thereto on the basis of their relative durations.
References Cited (Backward Citations)
US3969724A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-04 | 1988-06-04 | 1988-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-04 | 1992-06-04 | 1992-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-04 | 1996-06-04 | 1996-12-04 | $7700.00 | Window Closed / Lapsed |