Interface level programmability

Claim 2

An interface circuit comprising: a mode sensing circuit having an input terminal and first and second output terminals for producing control signals in response to an input signal, applied to the input terminal; a first output circuit, responsive to the control signals, to first data signal and to first and second states of the input signal, for producing a first output data signal dependent upon the first data signal when the input signal is in the first state and for producing the first output data signal dependent upon the first data signal and a circuit connected to the first output circuit when the input signal is in the second state; and a second output circuit, responsive to the control signals, to a second data signal, and to the first and second states of the input signal, for producing a second output data signal dependent upon the second data signal when the input signal is in the first state and for producing the second output data signal dependent upon the second data signal and a circuit connected to the second output circuit when the input signal is in the second state.

Claim 3

An interface circuit comprising: a mode sensing circuit having an input terminal and first and second output terminals for producing control signals in response to an input signal, applied to the input terminal; a first output circuit, responsive to the control signals, to a first data signal and to first and second states of the input signal, for producing a first output data signal dependent upon the first data signal when the input signal is in the first state and for producing the first output data signal dependent upon the first data signal and a circuit connected to the first output circuit when the input signal is in the second state, wherein the first output circuit comprises: first and second transistors having conducting paths connected in a series circuit between the input signal and ground, each of the first and second transistors having a control gate; first and second tri-statable inverters, each having an input terminal connected to one of a complementary pair of leads for the first data signal, an output terminal connected in common to the control gate of the first transistor, and a control terminal for connection to leads carrying opposite ones of the first and second states of the input signal; and a circuit for inverting the first data signal and applying it to a control gate of the second transistor which is connected to ground.

Claim 4

An interface circuit comprising: a mode sensing circuit having an input terminal and first and second output terminals for producing control signals in response to an input signal, applied to the input terminal; a first output circuit, responsive to the control signals, to a first data signal and to first and second states of the input signal, for producing a first output data signal dependent upon the first data signal when the input signal is in the first state and for producing the first output data signal dependent upon the first data signal and a circuit connected to the first output circuit when the input signal is in the second state, wherein the first output circuit comprises: first and second transistors having conducting paths connected in a series circuit between the input signal and ground, each of the first and second transistors having a control gate; first and second tri-statable inverters, each having an input terminal connected to one of a complementary pair of leads for the first data signal, an output terminal connected in common to the control gate of the first transistor, and a control terminal for connection to leads carrying opposite ones of the first and second states of the input signal; and a circuit for inverting the first data signal and applying it to a control gate of the second transistor which is connected to ground.