US4489246A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field effect transistor logic circuit having high operating speed and low power consumption
Assignee: Fujitsu Ltd
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Filing: 1981-12-16
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Granted: 1984-12-18
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Expires: 2001-12-16
Abstract
Abstract A logic circuit comprising a multi-input NOR gate, a plurality of load field-effect transistors (FET's) and a driving FET, the load FET's and driving FET being connected in series with each other between power sources and the logical output being derived from the connection points of the load FET's and the driving FET. The inputs of the NOR gate are the same as that of the load FET's. The inputs of the NOR gate are connected to the corresponding gates of the load FET's and the output of the NOR gate is connected to the gate of the driving FET.
Inventors
- 👤 Koichi Nishiuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443; H03K19/09445; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
330 words
A logic circuit having first and second power source terminals and a steady state, said logic circuit comprising: a plurality of first logic gate means for generating first logical output signals, each of said first logic gate means having at least one logical input terminal for receiving a logical input signal and generating one of the first logical output signals in response to the logical input signal; and second logic gate means, operatively coupled to said first logic gate means and having a logical output terminal, for generating a second logical output signal at the logical output terminal in response to the first logical output signals and the logical input signals and for cutting off a current path between the first and second power source terminals during the steady state, said second logic gate means comprising: a plurality of driving field effect transistors operatively coupled between said logical output terminal and the first power source terminal, each of said driving field effect transistors having a gate terminal supplied with one of said first logical output signals; and a plurality of load means operatively coupled between said logical output terminal and said second power source terminal, the number of said load means being equal to the number of said first logic gate means, each of said load means comprising at least one load field effect transistor, each of said load field effect transistors having a gate terminal supplied with a corresponding one of the first logical input signals of the corresponding one of said first logic gate means, the coupling of said driving field effect transistors between the logical output terminal and the first power source terminal being in parallel, and the coupling of said plurality of load means between the logical output terminal and the second power source terminal being in series, thereby cutting off a current path between the first and second power source terminals during the steady state in any logical state of said first logical input signals.
Claim 2
Dependent Claim
330 words
A logic circuit having first and second power source terminals and a steady state, said logic circuit comprising: a plurality of first logic gate means for generating first logical output signals, each of said first logic gate means having at least one logical input terminal for receiving a logical input signal and generating one of the first logical output signals in response to the logical input signal; and second logic gate means, operatively coupled to said first logic gate means and having a logical output terminal, for generating a second logical output signal at the logical output terminal in response to the first logical output signals and the logical input signals and for cutting off a current path between the first and second power source terminals during the steady state, said second logic gate means comprising: a plurality of driving field effect transistors operatively coupled between said logical output terminal and the first power source terminal, each of said driving field effect transistors having a gate terminal supplied with one of said first logical output signals; and a plurality of load means operatively coupled between said logical output terminal and said second power source terminal, the number of said load means being equal to the number of said first logic gate means, each of said load means comprising at least one load field effect transistor, each of said load field effect transistors having a gate terminal supplied with a corresponding one of the first logical input signals of the corresponding one of said first logic gate means, the coupling of said driving field effect transistors between the logical output terminal and the first power source terminal being in parallel, and the coupling of said plurality of load means between the logical output terminal and the second power source terminal being in series, thereby cutting off a current path between the first and second power source terminals during the steady state in any logical state of said first logical input signals.
Claim 3
Dependent Claim
43 words
A logic circuit as recited in claim 1, wherein each of said load means comprises a load field effect transistor corresponding to each logical input terminal where said load field effect transistors within each of said load means are operatively coupled in parallel.
Claim 4
Dependent Claim
329 words
A logic circuit having first and second power source terminals and a steady state, said logic circuit comprising: a plurality of first logic gate means for generating first logical output signals, each of said first logic gate means having at least one logical input terminal for receiving a logical input signal and generating one of the logical output signals in response to the logical input signal; and second logic gate means, operatively coupled to said first logic gate means and having a logical output terminal, for generating a second logical output signal at the logical output terminal in response to the first logical output signals and the logical input signals, and for cutting off a current path between the first and second power source terminals during the steady state, said second logic gate means comprising: a plurality of driving field effect transistors operatively coupled between said logical output terminal and the first power source terminal, each of said driving field effect transistors having a gate terminal supplied with one of said first logical output signals; and a plurality of load means operatively coupled between said logical output terminal and said second power source terminal, the number of said load means being equal to the number of said first logic gate means, each of said load means comprising at least one load field effect transistor, each of said load field effect transistors having a gate terminal supplied with a corresponding one of the first logical input signals of the corresponding one of said first logic gate means, the coupling of said driving field effect transistors between the logical output terminal and the first power source terminal being in series, and the coupling of said plurality of load means between the logical output terminal and the second power source terminal being in parallel, thereby cutting off a current path between the first and second power source terminals during the steady state in any logical state of said first logical input signals.
Claim 5
Dependent Claim
329 words
A logic circuit having first and second power source terminals and a steady state, said logic circuit comprising: a plurality of first logic gate means for generating first logical output signals, each of said first logic gate means having at least one logical input terminal for receiving a logical input signal and generating one of the logical output signals in response to the logical input signal; and second logic gate means, operatively coupled to said first logic gate means and having a logical output terminal, for generating a second logical output signal at the logical output terminal in response to the first logical output signals and the logical input signals, and for cutting off a current path between the first and second power source terminals during the steady state, said second logic gate means comprising: a plurality of driving field effect transistors operatively coupled between said logical output terminal and the first power source terminal, each of said driving field effect transistors having a gate terminal supplied with one of said first logical output signals; and a plurality of load means operatively coupled between said logical output terminal and said second power source terminal, the number of said load means being equal to the number of said first logic gate means, each of said load means comprising at least one load field effect transistor, each of said load field effect transistors having a gate terminal supplied with a corresponding one of the first logical input signals of the corresponding one of said first logic gate means, the coupling of said driving field effect transistors between the logical output terminal and the first power source terminal being in series, and the coupling of said plurality of load means between the logical output terminal and the second power source terminal being in parallel, thereby cutting off a current path between the first and second power source terminals during the steady state in any logical state of said first logical input signals.
Claim 6
Dependent Claim
57 words
A logic circuit as recited in claim 3, wherein each of said load means comprises a load field effect transistor, where said load field effect transistors in at least one of said load means are operatively coupled in parallel and said field effect transistors in at least one other of said load means are connected in series.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-18 | 1988-06-18 | 1988-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-18 | 1992-06-18 | 1992-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-18 | 1996-06-18 | 1996-12-18 | $7700.00 | Window Closed / Lapsed |