Method for synchronously transferring serial data to and from an input/output (I/O) module with true and complement error detection coding

Claim 1

A method for electrically isolating a first interface circuit and a second interface circuit having a first and second shift register respectively, the first and second interface circuits being connected by optical isolators, the method comprising the steps of: (a) loading the first shift register with 24-bit output data; (b) loading the second shift register with 24-bit input data; (c) transmitting a clock signal through a first optical isolator to provide a common clock signal for the first and second interface circuits to be received by the first and second shift registers; (d) clocking the output data from the first shift register, serially, in synchronism with the common clock signal, through a second optical isolator into the second shift register; (e) simultaneously with step (d) clocking the input data from the second shift register, serially, in synchronism with the common clock signal, through a third optical isolator into the first shift register; wherein the input data includes a fourteenth bit and a fifteenth bit that is the complement of the fourteenth bit and including the step of: (f) if the fourteenth and fifteenth bits of the input data as received by the first shift register after step (e) are not complements to each other generating a fault signal indicating failure of the third optical isolator; and (g) if the fourteenth and fifteenth bits of the input data as received by the first shift register after step (e) are complements to each other not generating a fault signal indicating failure of the third optical isolator.

Claim 2

A method for electrically isolating a first interface circuit and a second interface circuit having a first and second shift register respectively, the first and second interface circuits being connected by optical isolators, the method comprising the steps of: (a) loading the first shift register with 24-bit output data; (b) loading the second shift register with 24-bit input data; (c) transmitting a clock signal through a first optical isolator to provide a common clock signal for the first and second interface circuits to be received by the first and second shift registers; (d) clocking the output data from the first shift register, serially, in synchronism with the common clock signal, through a second optical isolator into the second shift register; (e) simultaneously with step (d) clocking the input data from the second shift register, serially, in synchronism with the common clock signal, through a third optical isolator into the first shift register; wherein the input data includes a fourteenth bit and a fifteenth bit that is the complement of the fourteenth bit and including the step of: (f) if the fourteenth and fifteenth bits of the input data as received by the first shift register after step (e) are not complements to each other generating a fault signal indicating failure of the third optical isolator; and (g) if the fourteenth and fifteenth bits of the input data as received by the first shift register after step (e) are complements to each other not generating a fault signal indicating failure of the third optical isolator.

Claim 3

A method for electrically isolating a first interface circuit and a second interface circuit having a first and second shift register respectively, the first and second interface circuits being connected by optical isolators, the method comprising the steps of: (a) loading the first shift register with 24-bit output data; (b) loading the second shift register with 24-bit input data; (c) transmitting a clock signal through a first optical isolator to provide a common clock signal for the first and second interface circuits to be received by the first and second shift registers; (d) clocking the output data from the first shift register, serially, in synchronism with the common clock signal, through a second optical isolator into the second shift register; (e) simultaneously with step (d) clocking the input data from the second shift register, serially, in synchronism with the common clock signal, through a third optical isolator into the first shift register; wherein the output data includes a fourteenth bit and a fifteenth bit that is the complement of the fourteenth bit and including the step of: (f) if the fourteenth and fifteenth bits of the output data as received by the second shift register after step (d) are not complements to each other generating a fault signal indicating failure to the second optical isolator; and (g) if the fourteenth and fifteenth bits of the output data as received by the second shift register after step (d) are complements to each other not generating a fault signal indicating failure of the second optical isolator.

Claim 4

A method for electrically isolating a first interface circuit and a second interface circuit having a first and second shift register respectively, the first and second interface circuits being connected by optical isolators, the method comprising the steps of: (a) loading the first shift register with 24-bit output data; (b) loading the second shift register with 24-bit input data; (c) transmitting a clock signal through a first optical isolator to provide a common clock signal for the first and second interface circuits to be received by the first and second shift registers; (d) clocking the output data from the first shift register, serially, in synchronism with the common clock signal, through a second optical isolator into the second shift register; (e) simultaneously with step (d) clocking the input data from the second shift register, serially, in synchronism with the common clock signal, through a third optical isolator into the first shift register; wherein the output data includes a fourteenth bit and a fifteenth bit that is the complement of the fourteenth bit and including the step of: (f) if the fourteenth and fifteenth bits of the output data as received by the second shift register after step (d) are not complements to each other generating a fault signal indicating failure to the second optical isolator; and (g) if the fourteenth and fifteenth bits of the output data as received by the second shift register after step (d) are complements to each other not generating a fault signal indicating failure of the second optical isolator.