Data transmission error detection in an electronic cash register system

Claim 1

Data error-checking apparatus for a digital transfer system, comprising: a first and a second data utilization unit, each utilization unit including a multi-bit shift register and a central processing unit coupled to said shift register via a bi-directional multi-bit parallel data bus, each of said central processing units further including a multi-bit memory having a capacity at least equal to that of said shift register whereby multi-bits of data defining a character are transferred in parallel between said memory and said shift register; a first serial data line coupled from an output of the shift register of the first utilization unit to an input of the shift register of the second utilization unit; and a second serial data line coupled from an output of the shift register of the second utilization unit to an input of the shift register of the second utilization unit, and wherein in a data error checking cycle, the bits of a first multi-bit data character are initially serially transferred from the shift register of said first utilization unit to the shift register of said second utilization unit, the bits of said first data character are also initially transferred to said memory of the central processing unit of said first utilization unit, and thereafter when a second multi-bit data character is serially transferred from the shift register of said first utilization unit to the shift register of said second utilization unit, said shift register simultaneously serially transfers said first data character back to the shift register of said first utilization unit, the starting time of the transfer of the first data character back to the first utilization unit being the same as that of the transfer of the second data character from said first utilization unit to the second utilization unit, wherein the central processing unit of said first utilization unit then compares said first data character stored in the memory of the central processing unit of said first utilization unit with said first data character transferred back to the shift register of said first utilization unit from the shift register of said second utilization unit, and wherein said central processing unit of the first utilization unit further determines whether or not the bits of the compared characters match and said central processing unit thereafter generates a first type output status signal when the compared characters are identical and generates a second type status signal when the compared characters are not identical.