US5267251A
Expired / Lapsed
US
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Line interface for a data transmission network
Assignee: Renault SA
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Filing: 1990-11-13
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Granted: 1993-11-30
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Expires: 2010-11-13
Abstract
Abstract A line interface for a two wire bus for detecting defects of the bus. The interface includes a shaping circuit having three comparators. The first comparator having two inputs connected to the two wires of the bus, the second comparator having a first input connected to one of the bus wires and another input connected to a reference signal, and the third comparator having a first input connected to the other wire of the bus and the second input connected to a reference signal. A first counter is connected to the output of the first comparator and counts a number of transitions which occur on the bus during a predetermined period of time. If the number of transitions detected by the first comparator is counted to be less than a predetermined number of transitions, the bus is defective. The second and third counters are respectively connected to the second and third comparators. Each of the second and third counters have inputs connected to outputs of the respective comparators and count the number of transitions on the output of the respective comparators. Each time there is a transition on the output of the second or third comparator, the third or second counter is reset. The comparators and counters are connected to circuitry which analyzes signals from the comparators and counters to determine defects on the bus and allow the transmission of data on only one of the bus wires if the other is defective.
Inventors
- 👤 Dominique Lenoir
- 👤 Jean-Michel Remaud
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:16
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/0264; H04L25/0292; G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/076; H04L12/00; H04L12/28; H04L12/40; H04L12/40006; H04L43/00; H04L12/40169; H04L2012/40267; H04L2012/40273; H04L25/0272
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
266 words
A line interface for a two wire bus, comprising: a shaping circuit including three comparators, each comparator having two inputs and one output, the first comparator having the two inputs thereof connected to the two wires of the bus, the second comparator having the first input thereof connected to one of said bus wires and the second input thereof connected to a first reference signal, the third comparator having the first input thereof connected to the other of bus wires and the second input thereof connected to a second reference signal; a first counter, connected to the output of the first comparator, for counting a number of transitions of the output of the first comparator during a period of time and generating on an output thereof, a defect signal if the counted number of transitions during the period of time is less than a predetermined number of transitions; second and third counters respective to the second and third comparators, each of the second and third counters having an input connected to the output of the respective comparator and counting a number of times there exists a predetermined signal from the output of the comparator connected thereto, the second counter being reset through a reset input thereof connected to the output of the third comparator, and the third counter being reset through a reset input thereof connected to the output of the second comparator; and bus defect determining means, connected to the outputs of the first, second, and third counters for determining a defect in the bus using the outputs of the first, second, and third counters.
Claim 2
Dependent Claim
266 words
A line interface for a two wire bus, comprising: a shaping circuit including three comparators, each comparator having two inputs and one output, the first comparator having the two inputs thereof connected to the two wires of the bus, the second comparator having the first input thereof connected to one of said bus wires and the second input thereof connected to a first reference signal, the third comparator having the first input thereof connected to the other of bus wires and the second input thereof connected to a second reference signal; a first counter, connected to the output of the first comparator, for counting a number of transitions of the output of the first comparator during a period of time and generating on an output thereof, a defect signal if the counted number of transitions during the period of time is less than a predetermined number of transitions; second and third counters respective to the second and third comparators, each of the second and third counters having an input connected to the output of the respective comparator and counting a number of times there exists a predetermined signal from the output of the comparator connected thereto, the second counter being reset through a reset input thereof connected to the output of the third comparator, and the third counter being reset through a reset input thereof connected to the output of the second comparator; and bus defect determining means, connected to the outputs of the first, second, and third counters for determining a defect in the bus using the outputs of the first, second, and third counters.
Claim 3
Dependent Claim
52 words
A line interface for a two wire bus according to claim 1, further comprising: a protocol manager for receiving a signal from the bus defect determining means which indicates a defect in the bus, and for controlling a protocol on the bus, depending on the signal from the bus defect determining means.
Claim 4
Dependent Claim
51 words
A line interface for a two wire bus according to claim 1, further comprising: a protocol manager having an input connected to the defect signal generated by the first counter, the protocol manager changing a mode of operation of the bus when the defect signal of the first counter is detected.
Claim 5
Dependent Claim
39 words
A line interface for a two wire bus according to claim 1, further comprising: a filter connected between the bus and the comparators, for converting analog signals on the bus to signals compatible with the inputs of the comparators.
Claim 6
Dependent Claim
54 words
A line interface for a two wire bus, according to claim 1, wherein the bus defect determining means comprises a defect decoding circuit, including: a plurality of NOR gates having inputs thereto connected the outputs of the second and third counters, the defect decoding circuit for indicating a type of defect on the bus.
Claim 7
Dependent Claim
42 words
A line interface for a two wire bus, according to claim 1, wherein the first counter further comprises: a reinitialization input for resetting a number of transitions counted by the first counter after said time period of the first counter has passed.
Claim 8
Dependent Claim
66 words
A line interface for a two wire bus, according to claim 1, further comprising: a selection circuit, connected to the bus defect determining means and the outputs of the second and third comparators, for enabling communication on only one of the two wires of the bus in response to an indicatons from the bus defect determining means that the other of said bus wires is defective.
Claim 9
Dependent Claim
23 words
A line interface for a two wire bus, according to claim 1, wherein the first and second reference signals are a same signal.
Claim 10
Dependent Claim
67 words
A line interface for a two wire bus, according to claim 1, further comprising: a filter means, connected between the outputs of the second and third comparators and the inputs of the second and third counters, for preventing changes to the inputs of the second and third counters unless the outputs of the second and third comparators maintain the outputs thereof for a predetermined number of cycles.
Claim 11
Dependent Claim
100 words
A line interface for a two wire bus according to claim 9, wherein the filter means comprises sequential D flip-flops, a first D flip-flop having an input thereof connected to the output of one of the second and third comparators and an output thereof connected to an input of a subsequent D flip flop, each output of each D flip-flop connected to inputs of an AND gate and a NOR gate, outputs of the AND and NOR gates connected to inputs of a JK flip-flop, the JK flip-flow having an output connected to one of the second and third counters.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-29 | 1997-05-31 | 1997-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-29 | 2001-05-31 | 2001-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-29 | 2005-05-31 | 2005-11-30 | $7700.00 | Window Closed / Lapsed |