Multi-stage serial-to-parallel/parallel-to-serial converter processing data words by segments

Claim 2

Circuit arrangement for at least one of converting data words having a parallel structure into data words having a serial structure or converting data words having a serial structure into data words having a parallel structure, comprising: a shift register converter having at least serial terminals and having a length less than a length of a data word to be converted, a data bus that connects parallel terminals via a plurality of registers to the serial terminals via the shift register converter, a plurality of control lines connecting an executive sequencer to the shift register converter and to the plurality of registers, the data word to be converted being divided into sections by the executive sequencer, these sections being, first, smaller than the data word length, and, second, corresponding to the length of the shift register converter, whereby these data word sections are successively converted in the shift register converter.

Claim 3

Circuit arrangement according to claim 1, wherein the plurality of registers are successively driven in that a register enable signal is shifted through register-associated control shift register stages that control the respective plurality of registers.

Claim 4

Circuit arrangement according to claim 2, wherein a first control shift register stage is supplied with the register enable signal at the beginning of a data word conversion.

Claim 5

Circuit arrangement according to claim 3, wherein the control shift register stages form a shift register closed in a ring.

Claim 6

Circuit arrangement according to claim 3, wherein the control shift register stages are each respectively formed by at least a series circuit of a first transmission gate, a first inverter, a second transmission gate, and a second inverter, whereby the second transmission gate is controlled with control signals that are complementary with respect to the control signal supplied to the first transmission gate.

Claim 7

A circuit arrangement for at least one of converting data words having a parallel structure into data words having a serial structure or converting data words having a serial structure into data words having a parallel structure, comprising: a shift register converter having at least serial terminals, a data bus that connects parallel terminals via a plurality of registers to the serial terminals via the shift register converter, a plurality of control lines connecting an executive sequencer to the shift register converter and to the plurality of registers, the data word to be converted being divided into sections by the executive sequencer, these sections being, first, smaller than the data word length, and, second, corresponding to the length of the shift register converter, whereby these data word sections are successively converted in the shift register converter, signals for controlling the plurality of registers being transmitted in a binary code from the executive sequence to the plurality of registers wherein the signals are decoded.

Claim 8

A circuit arrangement for at least one of converting data words having a parallel structure into data words having a serial structure or converting data words having a serial structure into data words having a parallel structure, comprising: a shift register converter having at least serial terminals, a data bus that connects parallel terminals via a plurality of registers to the serial terminals via the shift register converter, a plurality of control lines connecting an executive sequencer to the shift register converter and to the plurality of registers, the data word to be converted being divided into sections by the executive sequencer, these sections being, first, smaller than the data word length, and, second, corresponding to the length of the shift register converter, whereby these data word sections are successively converted in the shift register converter, signals for controlling the plurality of registers being transmitted in a binary code from the executive sequence to the plurality of registers wherein the signals are decoded.

Claim 9

Circuit arrangement according to claim 6, wherein the plurality of registers are successively driven in that a register enable signal is shifted through register-associated control shift register stages that control the respective plurality of registers.

Claim 10

Circuit arrangement according to claim 7, wherein a first control shift register stage is supplied with the register enable signal at the beginning of a data word conversion.

Claim 11

Circuit arrangement according to claim 8, wherein the control shift register stages form a shift register closed in a ring.

Claim 12

Circuit arrangement according to claim 8, wherein the control shift register stages are each respectively formed by at least a series circuit of a first transmission gate, a first inverter, a second transmission gate, and a second inverter, whereby the second transmission gate is controlled with control signals that are complementary with respect to the control signal supplied to the first transmission gate.