US4003083A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital data recording and decoding
Assignee: United States Department of the Navy
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Filing: 1975-04-15
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Granted: 1977-01-11
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Expires: 1995-04-15
Abstract
Abstract An economical system for both recording multiplexed digital data on a tape recorder and decoding the stored data.
Inventors
- 👤 Michael C. Gariazzo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:03
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
191 words
A system for multiplexing signals representative of digital data words for recording and thence their decoding, comprising: shift register means for converting said data signals from parallel to serial form; means for multiplexing and modulating said data signals for recording, said multiplexing means including: a counter; a one of eight decoder coupled to said counter; and a plurality of analog gates coupled to respective shift registers and said one of eight decoders; said modulating means including means for modulating said data signals at a first amplitude A 2 ; means for providing a unique output signal, said output signal modulated at a second amplitude A 1 ; means for detecting and demultiplexing said signals and said unique output signal for conversion into parallel form, said detecting means including a first, second, third and fourth operational amplifier, said first operational amplifier detecting only said unique output signal, said second operational amplifier detecting said signals representative of the data, said third operational amplifier enabling the control of the gain of said fourth operational amplifier whereby the gain of said fourth operational amplifier is adjusted to compensate for amplitude variations in the recording medium.
Claim 2
Independent Claim
191 words
A system for multiplexing signals representative of digital data words for recording and thence their decoding, comprising: shift register means for converting said data signals from parallel to serial form; means for multiplexing and modulating said data signals for recording, said multiplexing means including: a counter; a one of eight decoder coupled to said counter; and a plurality of analog gates coupled to respective shift registers and said one of eight decoders; said modulating means including means for modulating said data signals at a first amplitude A 2 ; means for providing a unique output signal, said output signal modulated at a second amplitude A 1 ; means for detecting and demultiplexing said signals and said unique output signal for conversion into parallel form, said detecting means including a first, second, third and fourth operational amplifier, said first operational amplifier detecting only said unique output signal, said second operational amplifier detecting said signals representative of the data, said third operational amplifier enabling the control of the gain of said fourth operational amplifier whereby the gain of said fourth operational amplifier is adjusted to compensate for amplitude variations in the recording medium.
Claim 3
Dependent Claim
65 words
A decoding system as recited in claim 1, wherein said multiplexing means further comprises: a clock; said counter counting down said clock; a NOR gate coupled to two outputs of said counter for providing said unique output signal to gate said data signals into respective shift registers; and a third output of said counter to clock said date from shift registers into respective analog gates.
Claim 4
Dependent Claim
103 words
A system as recited in claim 2 further including: said one of eight decoder coupled to three outputs of said counter for selecting a respective analog gate for multiplexing; means for attenuating the output of said clock at an amplitude of A 1 and A 2 ; modulating said unique output signal at said A 1 attenuated clock signal and said data signals at said A 2 attenuated clock signal; wherein said multiplexed output signal contains both the data signals at amplitude A 2 and said unique output signal at amplitude A 1 , wherein A 1 is greater than A 2 .
Claim 5
Dependent Claim
20 words
A decoding and decoding system as recited in claim 3 wherein said modulated unique output signal serves as synchronizing pulses.
Claim 6
Dependent Claim
53 words
A decoding and decoding system as recited in claim 4 further including: a counter and a shift register wherein the output of said second operational amplifier is supplied to said shift register and the output of said first operational amplifier is supplied to said counter, and wherein said counter clocks said shift register.
Claim 7
Dependent Claim
32 words
A decoding and decoding system as recited in claim 5 further including a phase lock loop, and a one of eight decoder coupled to said shift register for demultiplexing respective data signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-11 | 1980-07-12 | 1981-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-11 | 1984-07-12 | 1985-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-11 | 1988-07-12 | 1989-01-11 | $7700.00 | Window Closed / Lapsed |