US4620180A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Serial-to-parallel converter for high-speed bit streams
Assignee: Nortel Networks Ltd
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Filing: 1985-10-21
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Granted: 1986-10-28
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Expires: 2005-10-21
Abstract
Abstract A serial bit stream and a clock signal at a frequency equal to the bit rate divided by an integer n are passed in opposite directions via respective delay lines to respectively the data and clock inputs of n flip-flops, which thereby each latch a respective one of n bits of the bit stream during n/2 bit periods. During the next n/2 bit periods the outputs of the flip-flops are stable, and the n bits are latched in a parallel data latch. The delay lines comprise transmission lines terminated with their effective characteristic impedances. The converter is particularly useful for bit rates greater than 1Gb/s.
Inventors
- 👤 Stephen C. Carlton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:54
CPC Classifications
H; H03; H03M; H03M9/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
147 words
A serial-to-parallel converter comprising: a plurality n of data latches each having a clock input, a data input, and a data output; first and second delay lines coupled respectively to the data nputs and the clock inputs of the data latches; means for supplying a serial bit stream having a predetermined bit rate N to one end of the first delay line and a clock signal having a frequency N/n to an opposite end of the second delay line; and means for deriving parallel bits from the data outputs of the data latches; the delay lines comprising delay elements providing delays such that the total delay provided by the two delay lines between the data inputs and the clock inputs of any two aqjacent latches is 1/N, and the total delay provided in each delay line between the respective inputs of the atternate data latches is 1/N.
Claim 2
Dependent Claim
147 words
A serial-to-parallel converter comprising: a plurality n of data latches each having a clock input, a data input, and a data output; first and second delay lines coupled respectively to the data nputs and the clock inputs of the data latches; means for supplying a serial bit stream having a predetermined bit rate N to one end of the first delay line and a clock signal having a frequency N/n to an opposite end of the second delay line; and means for deriving parallel bits from the data outputs of the data latches; the delay lines comprising delay elements providing delays such that the total delay provided by the two delay lines between the data inputs and the clock inputs of any two aqjacent latches is 1/N, and the total delay provided in each delay line between the respective inputs of the atternate data latches is 1/N.
Claim 3
Dependent Claim
26 words
A converter as claimed in claim 1 wherein each delay line comprises n-1 delay elements coupled in series between the respective inputs of the data latches.
Claim 4
Dependent Claim
20 words
A converter as claimed in claim 2 wherein each delay element of each delay line provides a delay of 1/2N.
Claim 5
Dependent Claim
27 words
A converter as claimed in claim 3 wherein each delay element provides a delay of less than 500ps, the predetermined bit rate N being greater than 1Gb/s.
Claim 6
Dependent Claim
33 words
A converter as claimed in claim 1 wherein each delay line comprises alternately a delay element, providing a delay of 1/N, and a direct connection between the respective inputs of adjacent data latches.
Claim 7
Dependent Claim
18 words
A converter as claimed in claim 5 wherein each delay element provides a delay of less than 1ns.
Claim 8
Dependent Claim
21 words
A converter as claimed in claim 1 wherein each delay line comprises a transmission line terminated with its effective characteristic impedance.
Claim 9
Dependent Claim
15 words
A converter as claimed in claim 1 wherein each data latch comprises a D-type flip-flop.
Claim 10
Dependent Claim
39 words
A converter as claimed in claim 1 and including a further data latch, having n data inputs coupled to the data outputs of said data latches, for latching the parallel bits once in each cycle of the clock signal.
Claim 11
Dependent Claim
34 words
A converter as claimed in claim 1 and including a frequency divider for producing the clock signal oy frequency divison by a factor of n of a further clock signal having a frequency N.
Claim 12
Dependent Claim
15 words
A converter as claimed in claim 1 wherein n is an integral power of 2.
References Cited (Backward Citations)
US3955191A
Cited
US4443766A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-27 | 1990-04-28 | 1990-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-27 | 1994-04-28 | 1994-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-27 | 1998-04-28 | 1998-10-28 | $7700.00 | Window Closed / Lapsed |