Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
64 words
An interface device for synchronizing together an internally clocked modem and at least one data terminal equipment (DTE) each of said DTE being provided with a clock circuit for generating an external clock signal RC Ext, said interface including: a phase locked oscillator (PLO) provided with a control input and generating a recovered clock signal (XCO) to be used for adjusting said modem clock;
Claim 2
Dependent Claim
64 words
An interface device for synchronizing together an internally clocked modem and at least one data terminal equipment (DTE) each of said DTE being provided with a clock circuit for generating an external clock signal RC Ext, said interface including: a phase locked oscillator (PLO) provided with a control input and generating a recovered clock signal (XCO) to be used for adjusting said modem clock;
Claim 3
Dependent Claim
124 words
a switched clock generating circuit connected to said PLO and provided with one of said RC Ext signals for deriving a switched clock signal representative of the phase delay between said recovered clock signal and said one RC Ext signal; a first shift register provided with said one RC Ext signal and controlled by said switched clock signal for providing a shifted reference signal, said reference signal being applied to said PLO control input; a second shift register connected to said at least one DTE for receiving data therefrom, and controlled by said switched clock signal for shifting said data; and a gate connected to said second shift register and controlled by said recovered clock signal for providing in phase data to said modem.
Claim 4
Dependent Claim
124 words
a switched clock generating circuit connected to said PLO and provided with one of said RC Ext signals for deriving a switched clock signal representative of the phase delay between said recovered clock signal and said one RC Ext signal; a first shift register provided with said one RC Ext signal and controlled by said switched clock signal for providing a shifted reference signal, said reference signal being applied to said PLO control input; a second shift register connected to said at least one DTE for receiving data therefrom, and controlled by said switched clock signal for shifting said data; and a gate connected to said second shift register and controlled by said recovered clock signal for providing in phase data to said modem.
Claim 5
Dependent Claim
130 words
An interface device according to claim 1 wherein said switched clock generator includes: first generating means for generating a fast clock signal; second generating means for generating a slow clock signal; comparing the phases of said recovered clock signal and said external clock signal to derive phase delay information therefrom; first gating means connected to said first generating means and to said comparing means for gating said fast clock signal at the output of said switched clock generator during said phase delay and following the occurrence of a modem request to send; second gating means connected to said second generating means and to said first gating means for gating said slow clock signal at the output of said switched clock generator subsequently to said gating of said fast clock signal.
Claim 6
Dependent Claim
24 words
An interface citcuit according to claim 1 or 2 wherein said first shift register is provided with an inhibit output connected to said gate.
Claim 7
Dependent Claim
81 words
An interface circuit according to claim 1 or 2 wherein said PLO includes: a crystal oscillator; a frequency divider circuit the input of which is connected to said crystal oscillator and the output of which is made to provide said recovered clock signal, said divider being initially set to divide by a given factor; a phase comparing circuit for comparing said recovered clock signal with said reference signal, and for deriving therefrom information for adding or subtracting one unit to N.
Claim 8
Dependent Claim
79 words
An interface circuit according to claim 3 wherein said PLO includes: a crystal oscillator; a frequency divider circuit the input of which is connected to said crystal oscillator and the output of which is made to provide said recovered clock signal, said divider being initially set to divide by a given factor; a phase comparing circuit for comparing said recovered clock signal with said reference signal, and for deriving therefrom information for adding or subtracting one unit to N.