Enhanced universal asynchronous receiver-transmitter

Claim 2

A universal asynchronous receiver-transmitter device configured for connection to full-duplex means for low-speed serial receipt and transmission of data signals, the device having an internal bus and being selectably operable in a synchronous mode, the device comprising: a means for generating an asynchronous clock signal; a receive clock multiplexer means for receiving a synchrohous receive clock signal and said asynchronous clock signal and for generating a receive clock signal in response to a receive synchronous/asynchronous mode selection; a serial-to-parallel receive shift register means for receiving serial incoming data signals and said receive clock signal and generating parallel incoming data signals representative of said serial incoming data signals; a first-in, first-out receive register means for successively receiving said parallel incoming data siganls and storing a plurality of said parallel incoming data signals, said first-in, first-out receive register means successively introducing parallel received signals to said internal bus, each successive said parallel received signal respectively being representative of the earliest received parallel incoming data signal extant in said first-in, first-out receive register means; said first-in, first-out receive register means being programmable to define an incoming threshold number of said parallel incoming data signals which comprises said plurality of parallel incoming data signals; a transmit clock multiplexer means for receiving said synchronous receive clock signal and said asynchronous clock signal and for generating a transmit clock signal in response to a transmit synchronous/asynchronous mode selection; a first-in, first-out transmit register means for successively receiving parallel outgoing data signals from said internal bus and storing a plurality of said parallel outgoing data signals, said first-in, first-out transmit register means successively presenting parallel transmit signals at a FIFO transmit register output, each successive parallel transmit signal respectively being representative of the earliest received parallel outgoing data signal extant in said first-in, first-out transmit register means; said first-in, first-out transmit register means being programmable to define an outgoing threshold number of said parallel outgoing data signals which comprises said plurality of said parallel outgoing data signals; a parallel-to-serial transmit shift register means for receiving said transmit clock signal and said parallel transmit signals, said transmit shift register means generating serial outgoing data signals representative of said parallel transmit signals.

Claim 3

A universal asynchronous receiver-transmitter device as recited in claim 1 wherein the device further comprises addressable storage means for storing a plurality of special characters, and special character recognition means operatively connected to said addressable storage means, to said receive shift register and to said first-in, first-out receive register means for determining whether selected of said parallel incoming data signals correspond to any of said special characters, said special character recognition means generating a recognition signal indicating said determination.

Claim 4

A universal asunchronous receiver-transmitter device as recited in claim 2 wherein said first-in, first-out receive register means includes tagging means responsive to said recognition signal for tagging each of said parallel incoming data signals to indicate said determination, said tagging means generating a first tag signal indicative of said determination upon receipt of each of said parallel incoming data signals at said first-in, first-out receive register means, said tagging means generating a second tag signal for tagging each of said parallel received signals to indicate said determination.

Claim 5

A universal asynchronous receiver-transmitter device as recited in claim 3 wherein the device further comprises interface means connected to said internal bus for the connection of a microprocessor, and a plurality of status/control register means operably connected to said microprocessor interface, each of said plurality of register means comprising a plurality of bit storage locations, said plurality of bit storage locations storing a predetermined status/control condition of the device, said plurality of status/control register means including a line status register means receiving said first tag signal for setting a predetermined storage location in said line status register means according to said first tag signal, said plurality of status/control register means further including a UART status register means receiving said second tag signal for setting a predetermined storage location in said UART status register means according to said second tag signal.

Claim 6

A universal asynchronous receiver-transmitter device as recited in claim 4 wherein the device further comprises an interrupt generating means operatively connected to said UART status register means for generating an interrupt signal indicative of said second tag signal.

Claim 7

A universal asynchronous receiver-transmitter device as recited in claim 5 wherein said interrupt generating means includes an interrupt identification register means, said interrupt identification register means receiving said second tag signal for setting at least one of a plurality of predetermined interrupt source storage locations in said interrupt identification register means according to said second tag signal, said interrupt identification register means indicating reception of said second tag signal at a predetermined interrupt pending location in said interrupt identification register means.

Claim 8

A universal asynchronous receiver-transmitter device as recited in claim 6 wherein said first-in, first-out receive register means generates an incoming count signal indicating the number of said parallel incoming data signals stored in said first-in, first-out receive register means, and wherein said plurality of status/control register means further includes a UART control register means for storing threshold status signals, said UART control register means responding to receive FIFO threshold status signals from said microprocessor interface to store said receive FIFO threshold status signals in first predetermined storage locations in said UART control register means, and further wherein said interrupt identification register means responds to said receive FIFO threshold status signals stored in said UART control register and to said incoming count signal to set at least one of said plurality of interrupt source storage locations to indicate whether said plurality of parallel incoming data signals is less than said incoming threshold number.

Claim 9

A universal asynchronous receiver-transmitter device as recited in claim 7 wherein said first-in, first-out transmit register means generates an outgoing count signal indicating the number of said parallel outgoing data signals stored in said first-in, first-out transmit register means, and wherein said UART control register means further responding to transmit FIFO threshold status signals from said microprocessor interface to store said transmit FIFO threshold status signals in second predetermined storage locations in said UART control register means, and further wherein said interrupt identification register means responds to said transmit FIFO threshold status signals stored in said UART control register and said outgoing count signal to set at least one of said plurality of interrupt source storage locations to indicate whether said plurality of parallel outgoing data signals is less than said outgoing threshold number.

Claim 10

A universal asynchronous receiver-transmitter device as recited in claim 3 wherein the device further comprises parity testing means connected to said receive shift register and to said first-in, first-out receive register means for effecting a parity test for each of said parallel received signals and for generating a parity error signal representative of the result of each said parity test.

Claim 11

A universal asynchronous receiver-transmitter device configured for connection to full-duplex means for low-speed serial receipt and transmission of data signals, the device having an internal bus and being selectably operable in a synchronous mode, the device comprising: a means for generating an asynchronous clock signal; a receive clock multiplexer means for receiving a synchronous receive clock signal and said asynchronous clock signal and for generating a receive clock signal in response to a receive synchronous/asynchronous mode selection; a serial-to-parallel receive shift register means for receiving serial incoming data signals and said receive clock signal and generating parallel incoming data signals representative of said serial incoming data signals; a first-in, first-out receive register means for successively receiving said parallel incoming data signals and storing a plurality of said parallel incoming data signals, said first-in, first-out receive register means successively introducing parallel received signals to said internal bus, each successive said parallel received signal respectively being representative of the earliest received parallel incoming data signal extant in said first-in, first-out receive register means; said first-in, first-out receive register means being programmable to define an incoming threshold number of said parallel incoming data signals which comprises said plurality of parallel incoming data signals; a transmit clock multiplexer means for receiving said synchronous receive clock signal and said asynchronous clock signal and for generating a transmit clock signal in response to a transmit synchronous/asynchronous mode selection; a first-in, first-out transmit register means for successively receiving parallel outgoing data signals from said internal bus and storing a plurality of said parallel outgoing data signals, said first-in, first-out transmit register means successively presenting parallel transmit signals at a FIFO transmit register output, each successive parallel transmit signal respectively being representative of the earliest received parallel outgoing data signal extant in said first-in, first-out transmit register means; said first-in, first-out transmit register means being programmable to define an outgoing threshold number of said parallel outgoing data signals which comprises said plurality of said parallel outgoing data signals; a parallel-to-serial transmit shift register means for receiving said transmit clock signal and said parallel transmit signals, said transmit shift register means generating serial outgoing data signals representative of said parallel transmit signals; and addressable storage means for storing a plurality of special characters, and special character recognition means operatively connected to said addressable storage means, to said receive shift register and to said first-in, first-out receive register means for determining whether selected of said parallel incoming data signals correspond to any of said special characters, said special character recognition means generating a recognition signal indicating said determination.

Claim 12

A universal asynchronous receiver-transmitter device configured for connection to full-duplex means for low-speed serial receipt and transmission of data signals, the device having an internal bus and being selectably operable in a synchronous mode, the device comprising: a means for generating an asynchronous clock signal; a receive clock multiplexer means for receiving a synchronous receive clock signal and said asynchronous clock signal and for generating a receive clock signal in response to a receive synchronous/asynchronous mode selection; a serial-to-parallel receive shift register means for receiving serial incoming data signals and said receive clock signal and generating parallel incoming data signals representative of said serial incoming data signals; a first-in, first-out receive register means for successively receiving said parallel incoming data signals and storing a plurality of said parallel incoming data signals, said first-in, first-out receive register means successively introducing parallel received signals to said internal bus, each successive said parallel received signal respectively being representative of the earliest received parallel incoming data signal extant in said first-in, first-out receive register means; said first-in, first-out receive register means being programmable to define an incoming threshold number of said parallel incoming data signals which comprises said plurality of parallel incoming data signals; a transmit clock multiplexer means for receiving said synchronous receive clock signal and said asynchronous clock signal and for generating a transmit clock signal in response to a transmit synchronous/asynchronous mode selection; a first-in, first-out transmit register means for successively receiving parallel outgoing data signals from said internal bus and storing a plurality of said parallel outgoing data signals, said first-in, first-out transmit register means successively presenting parallel transmit signals at a FIFO transmit register output, each successive parallel transmit signal respectively being representative of the earliest received parallel outgoing data signal extant in said first-in, first-out transmit register means; said first-in, first-out transmit register means being programmable to define an outgoing threshold number of said parallel outgoing data signals which comprises said plurality of said parallel outgoing data signals; a parallel-to-serial transmit shift register means for receiving said transmit clock signal and said parallel transmit signals, said transmit shift register means generating serial outgoing data signals representative of said parallel transmit signals; and addressable storage means for storing a plurality of special characters, and special character recognition means operatively connected to said addressable storage means, to said receive shift register and to said first-in, first-out receive register means for determining whether selected of said parallel incoming data signals correspond to any of said special characters, said special character recognition means generating a recognition signal indicating said determination.

Claim 13

A universal asynchronous receiver-transmitter device as recited in claim 10 wherein said first-in, first-out receive register means includes tagging means responsive to said recognition signal for tagging each of said parallel incoming data signals to indicate said determination, said tagging means generating a first tag signal indicative of said determination upon receipt of each of said parallel incoming data signals at said first-in, first-out receive register means, said tagging generating a second tag signal for tagging each of said parallel received signals to indicate said determination.

Claim 14

A universal asynchronous receiver-transmitter device as recited in claim 11 wherein the device further comprises interface means connected to said internal bus for the connection of a microprocessor, and a plurality of status/control register means operably connected to said microprocessor interface, each of said plurality of register means comprising a plurality of bit storage locations, said plurality of bit storage locations storing a predetermined status/control condition of the device, said plurality of status/control register means including a line status register means receiving said first tag signal for setting a predetermined storage location in said line status register means according to said first tag signal, said plurality of status/control register means further including a UART status register means receiving said second tag signal for setting a predetermined storage location in said UART status register means according to said second tag signal.

Claim 15

A universal asynchronous receiver-transmitter device as recited in claim 12 wherein the device further comprises an interrupt generating means operatively connected to said UART status register means for generating an interrupt signal indicative of said second tag signal.

Claim 16

A universal asynchronous receiver-transmitter device as recited in claim 13 wherein said interrupt generating means includes an interrupt identification register means, said interrupt identification register means receiving said second tag signal for setting at least one of a plurality of predetermined interrupt source storage locations in said interrupt identification register means according to said second tag signal, said interrupt identification register means indicating reception of said second tag signal at a predetermined interrupt pending location in said interrupt identification register means.

Claim 17

A universal asynchronous receiver-transmitter device as recited in claim 14 wherein said first-in, first-out receive register means generates an incoming count signal indicating the number of said parallel incoming data signals stored in said first-in, first-out receive register means, and wherein said plurality of status/control register means further includes a UART control register means for storing threshold status signals, said UART control register means responding to receive FIFO threshold status signals from said microprocessor interface to store said receive FIFO threshold status signals in first predetermined storage locations in said UART control register means, and further wherein said interrupt identification register means responds to said receive FIFO threshold status signals stored in said UART control register and to said incoming count signal to set at least one of said plurality of interrupt source storage locations to indicate whether said plurality of parallel incoming data signals is less than said incoming threshold number.

Claim 18

A universal asynchronous receiver-transmitter device as recited in claim 15 wherein said first-in, first-out transmit register means genetates an outgoing count signal indicating the number of said parallel outgoing data signals stored in said first-in, first-out transmit register means, and wherein said UART control register means further responding to transmit FIFO threshold status signals from said microprocessor interface to store said transmit FIFO threshold status signals in second predetermined storage locations in said UART control register means, and further wherein said interrupt identificaion register means responds to said transmit FIFO threshold status signals stored in said UART control register and said outgoing count signal to set at least one of said plurality of interrupt source storage locations to indicated whether said plurality of parallel outgoing data signals is less than said outgoing threshold number.

Claim 19

A universal asynchronous receiver-transmitter device as recited in claim 11 wherein the device further comprises parity testing means connected to said receive shift register and to said first-in, first-out receive register means for effecting a parity test for each of said parallel received signals and for generating a parity error signal representative of the result of each said parity test.