US5550781A
Expired / Lapsed
US
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Semiconductor apparatus with two activating modes of different number of selected word lines at refreshing
Assignee: Hitachi Ltd
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Filing: 1995-01-31
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Granted: 1996-08-27
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Expires: 2015-01-31
Abstract
Abstract A memory cartridge having a plurality of dynamic memory units includes an access conversion circuit which converts a static access signal into its inverted signal and an access control circuit which controllably switches between a signal for refreshing each dynamic unit and a signal for external access. The memory cartridge also includes a power switching circuit which switches power from an internal power supply to an external power supply when the memory cartridge is mounted to an external device.
Inventors
- 👤 Ken Sugawara
- 👤 Shigeru Sakairi
- 👤 Mikio Matoba
- 👤 Toshio Sasaki
- 👤 Katsuhiro Shimohigashi
- 👤 Katsutaka Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 16:13
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/4063; G11C11/407; G11C11/4074; G11C5/00; G11C5/14; G11C5/141; G11C5/143; G11C5/147
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
141 words
A semiconductor apparatus comprising: a plurality of word lines; a plurality of bit lines, each crossing with said plurality of word lines; a plurality of memory cells, each provided at any crossing points of said plurality of bit lines and said plurality of word lines; and a word line activation signal generating circuit for generating a signal activating any of said plurality of word lines, said word line activation signal generating circuit having a first mode of activating at least two of said plurality of word lines substantially at the same time to refresh information of memory cells connected to said activated at least two of said plurality of word lines and a second mode of activating each of said plurality of word lines, one by one, to refresh information of memory cells connected to said activated plurality of word lines.
Claim 2
Dependent Claim
141 words
A semiconductor apparatus comprising: a plurality of word lines; a plurality of bit lines, each crossing with said plurality of word lines; a plurality of memory cells, each provided at any crossing points of said plurality of bit lines and said plurality of word lines; and a word line activation signal generating circuit for generating a signal activating any of said plurality of word lines, said word line activation signal generating circuit having a first mode of activating at least two of said plurality of word lines substantially at the same time to refresh information of memory cells connected to said activated at least two of said plurality of word lines and a second mode of activating each of said plurality of word lines, one by one, to refresh information of memory cells connected to said activated plurality of word lines.
Claim 3
Dependent Claim
26 words
A semiconductor apparatus according to claim 1, further comprising a control circuit for switching between said first and second modes in response to an input signal.
Claim 4
Dependent Claim
69 words
A semiconductor apparatus according to claim 1, further comprising: a control circuit for switching between said first and second modes; an auxiliary power source connected to a terminal of said semiconductor apparatus; and a detection circuit for detecting failure in a main power source of said semiconductor apparatus; wherein said control circuit switches between said first and second modes in response to an output signal of said detection circuit.
Claim 5
Dependent Claim
33 words
A semiconductor apparatus according to claim 1, wherein a refresh period of a refreshing operation of said second mode is shorter than a refresh period of a refreshing operation of said first mode.
Claim 6
Dependent Claim
16 words
A semiconductor apparatus according to claim 1, wherein said plurality of memory cells are dynamic storages.
Claim 7
Dependent Claim
167 words
A semiconductor apparatus comprising: first and second memory arrays, each including a plurality of word lines, a plurality of bit lines, each crossing with said plurality of word lines, and a plurality of memory cells, each provided at any crossing points of said plurality of bit lines and said plurality of word lines; and a word line activation signal generating circuit for generating a signal activating any of said plurality of word lines, said word line activation signal generating circuit having a first mode of activating one of said plurality of word lines of said first memory array and one of said plurality of word lines of said second memory array substantially at the same time to refresh information of memory cells connected to said activated plurality of word lines and a second mode of activating each of said plurality of word lines of said first and second memory arrays one by one to refresh information of memory cells connected to said activated plurality of word lines.
Claim 8
Dependent Claim
167 words
A semiconductor apparatus comprising: first and second memory arrays, each including a plurality of word lines, a plurality of bit lines, each crossing with said plurality of word lines, and a plurality of memory cells, each provided at any crossing points of said plurality of bit lines and said plurality of word lines; and a word line activation signal generating circuit for generating a signal activating any of said plurality of word lines, said word line activation signal generating circuit having a first mode of activating one of said plurality of word lines of said first memory array and one of said plurality of word lines of said second memory array substantially at the same time to refresh information of memory cells connected to said activated plurality of word lines and a second mode of activating each of said plurality of word lines of said first and second memory arrays one by one to refresh information of memory cells connected to said activated plurality of word lines.
Claim 9
Dependent Claim
26 words
A semiconductor apparatus according to claim 6, further comprising a control circuit for switching between said first and second modes in response to an input signal.
Claim 10
Dependent Claim
69 words
A semiconductor apparatus according to claim 6, further comprising: a control circuit for switching between said first and second modes; an auxiliary power source connected to a terminal of said semiconductor apparatus; and a detection circuit for detecting failure in a main power source of said semiconductor apparatus; wherein said control circuit switches between said first and second modes in response to an output signal of said detection circuit.
Claim 11
Dependent Claim
33 words
A semiconductor apparatus according to claim 6, wherein a refresh period of a refreshing operation of said second mode is shorter than a refresh period of a refreshing operation of said first mode.
Claim 12
Dependent Claim
16 words
A semiconductor apparatus according to claim 6, wherein said plurality of memory cells are dynamic storages.
Claim 13
Dependent Claim
44 words
A memory apparatus comprising: a plurality of memory chips starting a refresh operation in response to respective input refresh control signals; and a refresh control circuit providing said respective refresh control signals at mutually different times for each of said plurality of memory chips.
Claim 14
Dependent Claim
44 words
A memory apparatus comprising: a plurality of memory chips starting a refresh operation in response to respective input refresh control signals; and a refresh control circuit providing said respective refresh control signals at mutually different times for each of said plurality of memory chips.
Claim 15
Dependent Claim
16 words
A memory apparatus according to claim 11, wherein said plurality of memory chips are dynamic storages.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-27 | 2000-02-26 | 2000-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-27 | 2004-02-26 | 2004-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-27 | 2008-02-26 | 2008-08-27 | $7700.00 | Window Closed / Lapsed |