US4901283A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random-access memory system with power-up and power-down refresh circuits
Assignee: Fujitsu Services Ltd
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Filing: 1988-11-02
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Granted: 1990-02-13
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Expires: 2008-11-02
Abstract
Abstract A dynamic random-access memory (DRAM) has a first refresh circuit for producing memory refreshes during power-up, and a second refresh circuit for producing memory refreshes during power-down. The power-down refresh circuit is powered by a battery, and has a lower power consumption than the power-up circuit. During transition from power-down to power-up, the frequency of refreshing is doubled for a short period, so as to build up a surplus of refreshes. This allows refreshing to stop while the first or power-up refresh circuit is brought back into operation.
Inventors
- 👤 Jonathan M. Hanbury
- 👤 Keith Burton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:09
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
159 words
A dynamic random-access memory system comprising: (a) a dynamic random-access memory, (b) means for generating control signals defining a power-down condition, a transition condition, and a power-up condition, (c) a power-down refresh circuit, responsive to said control signals, for producing a series of refresh signals at a first predetermined frequency in the power-down condition and at a second predetermined frequency in the transition condition, the second predetermined frequency being higher that the first predetermined frequency, (d) a power-up refresh circuit for producing a series of refresh signals in the power-up condition, the power-up refresh circuit having a higher power requirement than the power-down refresh circuit, and (e) selection means, responsive to said control signals, for selecting refresh signals from the power-down refresh circuit to determine refresh cycles for the memory during the power-down condition and the transition condition, and for selecting refresh signals from the power-up refresh circuit to determine refresh cycles for the memory during the power-up condition.
Claim 2
Dependent Claim
159 words
A dynamic random-access memory system comprising: (a) a dynamic random-access memory, (b) means for generating control signals defining a power-down condition, a transition condition, and a power-up condition, (c) a power-down refresh circuit, responsive to said control signals, for producing a series of refresh signals at a first predetermined frequency in the power-down condition and at a second predetermined frequency in the transition condition, the second predetermined frequency being higher that the first predetermined frequency, (d) a power-up refresh circuit for producing a series of refresh signals in the power-up condition, the power-up refresh circuit having a higher power requirement than the power-down refresh circuit, and (e) selection means, responsive to said control signals, for selecting refresh signals from the power-down refresh circuit to determine refresh cycles for the memory during the power-down condition and the transition condition, and for selecting refresh signals from the power-up refresh circuit to determine refresh cycles for the memory during the power-up condition.
Claim 3
Dependent Claim
57 words
A system according to claim 1 further including means for operating the power-up refresh circuit to produce refresh signals at said second predetermined frequency for a predetermined time period upon commencement of said power-up condition, and means for operating the power-up refresh circuit to produce refresh signals at said first predetermined frequency following said predetermined time period.
Claim 4
Dependent Claim
17 words
A system according to claim 1 wherein said second predetermined frequency is twice said first predetermined frequency.
Claim 5
Independent Claim
223 words
A method of operating a dynamic random-access memory system comprising a dynamic random-access memory, a main power supply, a back-up power supply, a power-up refresh circuit, and a power-down refresh circuit having a lower power requirement than the power-up refresh circuit, the method comprising: (a) operating the system in a power-down condition in which the main power supply is inactive and the power-down refresh circuit receives power from the back-up power supply, (b) in the power-down condition, operating the power-down refresh circuit to supply refresh signals to the memory at a first predetermined frequency, to determine refresh cycles for the memory, (c) activating the main power supply, (d) during a first transitional period following activation of the main power supply, operating the power-down refresh circuit to supply refresh signals to the memory at a second predetermined frequency, higher than the first predetermined frequency, (e) during a second transitional period following said first period, initializing said power-up refresh circuit, without supplying any refresh signals to the memory, (f) during a third transitional period, following the second period, operating the power-up refresh circuit to supply refresh signals to the memory at said second predetermined frequency, and (g) following said third period, operating the system in a power-up condition, in which the power-up refresh circuit supplies refresh signals to the memory at said first predetermined frequency.
Claim 6
Independent Claim
223 words
A method of operating a dynamic random-access memory system comprising a dynamic random-access memory, a main power supply, a back-up power supply, a power-up refresh circuit, and a power-down refresh circuit having a lower power requirement than the power-up refresh circuit, the method comprising: (a) operating the system in a power-down condition in which the main power supply is inactive and the power-down refresh circuit receives power from the back-up power supply, (b) in the power-down condition, operating the power-down refresh circuit to supply refresh signals to the memory at a first predetermined frequency, to determine refresh cycles for the memory, (c) activating the main power supply, (d) during a first transitional period following activation of the main power supply, operating the power-down refresh circuit to supply refresh signals to the memory at a second predetermined frequency, higher than the first predetermined frequency, (e) during a second transitional period following said first period, initializing said power-up refresh circuit, without supplying any refresh signals to the memory, (f) during a third transitional period, following the second period, operating the power-up refresh circuit to supply refresh signals to the memory at said second predetermined frequency, and (g) following said third period, operating the system in a power-up condition, in which the power-up refresh circuit supplies refresh signals to the memory at said first predetermined frequency.
Claim 7
Dependent Claim
17 words
A method according to claim 4 wherein said second predetermined frequency is twice said first predetermined frequency.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-12 | 1993-08-14 | 1994-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-12 | 1997-08-14 | 1998-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-12 | 2001-08-14 | 2002-02-13 | $7700.00 | Window Closed / Lapsed |