US4625296A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory refresh circuit with varying system transparency
Assignee: Concurrent Computer Corp
•
Filing: 1984-01-17
•
Granted: 1986-11-25
•
Expires: 2004-01-17
Abstract
Abstract A memory refresh circuit controls the refreshing of dynamic RAM included in a system wherein a control store outputs micro-code instructions to control the system operation in response to sequences specified by a sequence and interrupt logic circuit (SIL). A counter transmits certain counts of system machine cycles to an array logic device. In response to one count, the array logic device generates a memory refresh request signal which is applied to a RAM address logic circuit (RAL). The RAL monitors the micro-code instruction output at each machine cycle to determine whether the instruction will access the dynamic RAM during that machine cycle, and if no memory access is detected, the RAL generates a signal to initiate a memory refresh operation, which operation requires two machine cycles to complete. The array logic device also monitors the micro-code instructions to determine if and when a refresh operation was initiated. If the refresh operation was initiated, the array logic determines whether the instruction in the following machine cycle needs to access the dynamic RAM. If it does, the array logic device generates a freeze clock signal which causes the SIL to freeze the execution of the instruction until the refresh is complete, i.e. this refresh will be partially transparent. Alternatively, if no refresh has been initiated after a specified number of machine cycles, the array logic device generates an interrupt signal. In response to this interrupt, the SIL causes the control store to execute a pair of NOP instructions to cause an uninterrupted refresh operation.
Inventors
- 👤 Joseph S. Shriver
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:55
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
285 words
In a system including a clock source for generating a clock signal, a system machine cycle being determined by reference to the clock signal, a refreshable memory means, a sequence and interrupt logic circuit, and a control store for producing micro-code instruction signals each system machine cycle in response to addresses generated by the sequence and interrupt logic circuit, a memory refresh request circuit comprising, in combination: a counter, responsive to the clock signal, for producing at least one count signal representing at least one count of the clock signal, the counter also being responsive to a clock reset signal to reset the counter; an array logic device, responsive to the at least one count and to the micro-code instruction signals, (a) for producing a memory refresh request signal and the clock reset signal when a specified count has been achieved, (b) for producing a freeze clock signal to block further sequencing of the sequence and interrupt logic circuit during a machine cycle referred to as an after cycle, which after cycle follows a machine cycle referred to as a start cycle, when the micro-code instruction signal to be executed during the after cycle requires an access to the memory means, a start cycle being determined by the array logic device to occur when the memory refresh request signal has been produced and the micro-code instruction signal to be executed during that machine cycle does not require an access to the memory means, and (c) for producing an interrupt signal which is input into the sequence and logic circuit when a second specified count has been achieved after the memory refresh request signal has been produced without a start cycle being determined to have occurred.
Claim 2
Dependent Claim
285 words
In a system including a clock source for generating a clock signal, a system machine cycle being determined by reference to the clock signal, a refreshable memory means, a sequence and interrupt logic circuit, and a control store for producing micro-code instruction signals each system machine cycle in response to addresses generated by the sequence and interrupt logic circuit, a memory refresh request circuit comprising, in combination: a counter, responsive to the clock signal, for producing at least one count signal representing at least one count of the clock signal, the counter also being responsive to a clock reset signal to reset the counter; an array logic device, responsive to the at least one count and to the micro-code instruction signals, (a) for producing a memory refresh request signal and the clock reset signal when a specified count has been achieved, (b) for producing a freeze clock signal to block further sequencing of the sequence and interrupt logic circuit during a machine cycle referred to as an after cycle, which after cycle follows a machine cycle referred to as a start cycle, when the micro-code instruction signal to be executed during the after cycle requires an access to the memory means, a start cycle being determined by the array logic device to occur when the memory refresh request signal has been produced and the micro-code instruction signal to be executed during that machine cycle does not require an access to the memory means, and (c) for producing an interrupt signal which is input into the sequence and logic circuit when a second specified count has been achieved after the memory refresh request signal has been produced without a start cycle being determined to have occurred.
Claim 3
Dependent Claim
257 words
The memory refresh circuit of claim 1 wherein the array logic device comprises: first means, responsive to the at least one count, for producing the memory refresh request signal when said specified count has been achieved, the first means also being responsive to a refresh reset signal to clear the memory refresh request signal; second means, responsive to the memory refresh request signal, for generating the clock reset signal; third means, responsive to the memory refresh request signal and to the micro-code instruction signals, for producing a memory refresh started indication signal when the micro-code instruction signal to be executed during a machine cycle does not require an access to the memory means and the memory refresh request signal is active, which machine cycle is referred to as the start cycle; fourth means, responsive to the memory refresh started indication signal and to the micro-code instruction signals in the machine cycle following the start cycle, which machine cycle is the after cycle, for producing the freeze clock signal which is applied to the sequence and interrupt logic circuit to block further sequencing thereof during the after cycle when the micro-code instruction signal to be executed during the after cycle requires an access to the memory means; fifth means, responsive to the memory refresh started indication signal during the after cycle, for producing the refresh reset signal; and sixth means, responsive to the memory refresh request signal and to the second specified count signal, for producing the interrupt signal which is input into the sequence and logic circuit.
Claim 4
Dependent Claim
31 words
The memory refresh circuit of claim 2 wherein the clock signal comprises clock pulses, the time interval between two clock pulses being substantially equal to the time of a machine cycle.
Claim 5
Dependent Claim
32 words
The memory refresh circuit of claim 3 wherein the counter provides a binary count signal on a plurality of output lines, which binary count signal represents the binary count in the counter.
Claim 6
Dependent Claim
36 words
The memory refresh circuit of claim 4 wherein the first means is responsive to at least two output lines from the counter to produce the memory refresh request signal when two output lines are simultaneously active.
Claim 7
Dependent Claim
31 words
The memory refresh circuit of claim 5 wherein the third means is responsive to selected ones of the micro-code instruction signals which do not require an access to the memory means.
Claim 8
Dependent Claim
28 words
The memory refresh circuit of claim 6 wherein the fourth means is responsive selected ones of the micro-code instruction signals which require an access to the memory means.
Claim 9
Dependent Claim
79 words
The memory refresh circuit of claim 1 wherein the system further comprises a RAM address logic circuit, responsive to the memory refresh reqeust signal and to the micro-code instruction signals, for producing a memory refresh signal when the micro-code instruction signal to be executed during a machine cycle does not require an access to the memory means and the memory refresh request signal is active, in response to which memory refresh signal the memory means initiates a refresh operation.
Claim 10
Dependent Claim
79 words
The memory refresh circuit of claim 2 wherein the system further comprises a RAM address logic circuit, responsive to the memory refresh request signal and to the micro-code instruction signals, for producing a memory refresh signal when the micro-code instruction signal to be executed during a machine cycle does not require an access to the memory means and the memory refresh request signal is active, in response to which memory refresh signal the memory means initiates a refresh operation.
References Cited (Backward Citations)
US3760379A
Cited
US4106108A
Cited
US4172282A
Cited
US4218753A
Cited
US4204254A
Cited
US4249247A
Cited
US4317169A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-24 | 1990-05-26 | 1990-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-24 | 1994-05-26 | 1994-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-24 | 1998-05-26 | 1998-11-25 | $7700.00 | Window Closed / Lapsed |