US4313180A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Refresh system for a dynamic memory
Assignee: Sharp Corp
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Filing: 1980-01-30
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Granted: 1982-01-26
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Expires: 2000-01-30
Abstract
Abstract An electronic apparatus comprises a central processor unit (CPU) for controlling the operation of the electronic apparatus, and a dynamic random access memory (RAM). The CPU develops a refresh control signal for refreshing the memory data stored in the dynamic RAM. An additional refresh control circuit is provided outside of the CPU for developing another refresh control signal. The additional refresh control circuit is connected to receive the electric power from a backup battery included in the electronic apparatus. When the service interruption occurs, the additional refresh control circuit is enabled to maintain the memory data stored in the dynamic RAM.
Inventors
- 👤 Daisuke Mochizuki
- 👤 Shigeru Kitano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:40
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C5/00; G11C5/14; G11C5/141; H; H02; H02J; H02J9/00; H02J9/04; H02J9/06
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
306 words
A refresh control system for a dynamic memory in an electronic apparatus powered by a main power source, said refresh control system comprising: a central processor unit including a first refresh control signal developing means powered by said main power source for developing a first refresh control signal; second refresh control signal developing means separate from said central processor unit and capable of being powered by an auxiliary power source for developing a second refresh control signal, said auxiliary power source providing power to said second refresh control signal developing means when the power to said first refresh control signal developing means has been interrupted, said second refresh control signal developing means including oscillator means, timing counter means responsive to the output of said oscillator means for developing a plurality of timing signals, holding circuit means connected between said oscillator means and said timing counter means for holding the output of said timing counter means at its current value following the restoration of the supply power to the first refresh control signal developing means, and further means responsive to the timing signals from the timing counter means for developing said second refresh control signal; determination means responsive to the power supplied by the main power source and by the auxiliary power source for detecting whether the power from the main power source being supplied to the first refresh control signal developing means has been interrupted and for developing a first control signal when the power has not been interrupted and developing a second control signal when the power has been interrupted; and selection control means responsive to the first and second control signals for enabling said first refresh control signal developing means in response to said first control signal and for enabling said second refresh control signal developing means in response to said second control signal.
Claim 2
Dependent Claim
306 words
A refresh control system for a dynamic memory in an electronic apparatus powered by a main power source, said refresh control system comprising: a central processor unit including a first refresh control signal developing means powered by said main power source for developing a first refresh control signal; second refresh control signal developing means separate from said central processor unit and capable of being powered by an auxiliary power source for developing a second refresh control signal, said auxiliary power source providing power to said second refresh control signal developing means when the power to said first refresh control signal developing means has been interrupted, said second refresh control signal developing means including oscillator means, timing counter means responsive to the output of said oscillator means for developing a plurality of timing signals, holding circuit means connected between said oscillator means and said timing counter means for holding the output of said timing counter means at its current value following the restoration of the supply power to the first refresh control signal developing means, and further means responsive to the timing signals from the timing counter means for developing said second refresh control signal; determination means responsive to the power supplied by the main power source and by the auxiliary power source for detecting whether the power from the main power source being supplied to the first refresh control signal developing means has been interrupted and for developing a first control signal when the power has not been interrupted and developing a second control signal when the power has been interrupted; and selection control means responsive to the first and second control signals for enabling said first refresh control signal developing means in response to said first control signal and for enabling said second refresh control signal developing means in response to said second control signal.
Claim 3
Dependent Claim
44 words
A refresh control system in accordance with claim 1, wherein the second control signal is developed in response to the power supplied by the auxiliary power source, the first control signal being developed in response to the power supplied by the main power source.
Claim 4
Dependent Claim
23 words
The refresh control system of claim 1, wherein said auxiliary power source comprises a battery included in said electronic apparatus for backup purposes.
Claim 5
Dependent Claim
49 words
The refresh control system of claim 3 or 1, wherein said holding circuit means holds the output signals derived from said second refresh control signal developing means for a predetermined period of time following the restoration of the supply of power to the first refresh control signal developing means.
Claim 6
Dependent Claim
58 words
The refresh control system of claims 3 or 1, wherein said further means comprises: decoder means responsive to said timing signals for developing refresh address selection signals; and refresh pulse source means for developing said second refresh control signal in response to said timing signals derived from said timing counter means and to said refresh address selection signals.
Claim 7
Dependent Claim
30 words
The refresh control system of claim 5, wherein said refresh pulse source means further comprises a differentiation circuit for differentiating one of said timing signals derived from said timing counter.
Claim 8
Dependent Claim
42 words
The refresh control system of claim 5, wherein said holding circuit means comprises a latch circuit connected to receive an output signal developed from said oscillator means, said timing counter being connected to receive an output signal developed from said latch circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-01-25 | 1985-07-27 | 1986-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-01-25 | 1989-07-27 | 1990-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-01-25 | 1993-07-27 | 1994-01-26 | $7700.00 | Window Closed / Lapsed |