EP0128427A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory having circuit effecting refresh on variable cycles
Assignee: Hitachi Ltd
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Filing: 1984-05-24
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Granted: —
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Expires: 2004-05-24
Abstract
Abstract in a semiconductor memory using a dynamic memory device (24), a battery (17a ... 17c) supplies a power source voltage and a substrate bias voltage when the memory is cut off from an external device, and a refresh control circuit (22) changes the refresh timing of the memory device (24) in accordance with the leakage current of the memory device (24). The power consumption of the memory can thus be reduced and the data can be kept for an extended period without an external power source.
Inventors
- 👤 Shimohigashi Katsuhiro
- 👤 Kubo Masaharu
- 👤 Miyauchi Katsuki
- 👤 Masuhara Toshiaki
- 👤 Minato Osamu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 18:09
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/4063; G11C11/407; G11C11/4072; G11C11/4074; G11C5/00; G11C5/14; G11C5/141
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
9 words
A refresh control circuit for a dynamic memory array
Claim 2
Dependent Claim
9 words
A refresh control circuit for a dynamic memory array
Claim 3
Dependent Claim
91 words
(24) having a first capacitor portion for keeping the data, comprising: a second capacitor (C) portion having the construction substantially the same as that of said first capacitor portion; means (32) for detecting the potential change of said capacitor portion (C) due to a leakage current (IL) and producing timing signals when the change reaches a certain value; means (33) for supplying refresh signals to said memory array (24) in response to said timing signal; and means (T1) for charging said second capacitor portion (C) in response to said timing signal.
Claim 4
Dependent Claim
91 words
(24) having a first capacitor portion for keeping the data, comprising: a second capacitor (C) portion having the construction substantially the same as that of said first capacitor portion; means (32) for detecting the potential change of said capacitor portion (C) due to a leakage current (IL) and producing timing signals when the change reaches a certain value; means (33) for supplying refresh signals to said memory array (24) in response to said timing signal; and means (T1) for charging said second capacitor portion (C) in response to said timing signal.
Claim 5
Dependent Claim
73 words
The refresh control circuit as defined in claim 1 wherein said memory includes further: a first battery (17a, 17b) for supplying operation power source to a dynamic memory device (24) when said memory is not connected to an external device reading and writing said dynamic memory device and supplying power source to said dynamic memory device; and a second battery (17c) for supplying a substrate bias voltage to said dynamic memory device (24).
Claim 6
Dependent Claim
68 words
A memory comprising: a memory device (24); a voltage generation circuit (6) for converting a power source voltage supplied from an external device reading and writing said memory device (24) and supplying operation power source to said memory device (24), and generating a substrate bias voltage; and a battery (17c) for supplying said substrate bias voltage when the operation power source is not supplied from said external device.
Claim 7
Dependent Claim
68 words
A memory comprising: a memory device (24); a voltage generation circuit (6) for converting a power source voltage supplied from an external device reading and writing said memory device (24) and supplying operation power source to said memory device (24), and generating a substrate bias voltage; and a battery (17c) for supplying said substrate bias voltage when the operation power source is not supplied from said external device.
Claim 8
Dependent Claim
106 words
A memory including a memory device (24) and a battery (17a...17c) for supplying operation power to said memory device (24), characterised by a change-over device (1, 2) detecting whether or not said memory is connected to an external device reading and writing said memory device and supplying operating power to said memory device, the change-over device (1, 2) causing said external device to supply the operation power to said memory device (24) when said memory is connected to said external device, and causing said battery (17a...17c) to supply the operation power to said memory device (24) when said memory is not connected to said external device.
Claim 9
Dependent Claim
106 words
A memory including a memory device (24) and a battery (17a...17c) for supplying operation power to said memory device (24), characterised by a change-over device (1, 2) detecting whether or not said memory is connected to an external device reading and writing said memory device and supplying operating power to said memory device, the change-over device (1, 2) causing said external device to supply the operation power to said memory device (24) when said memory is connected to said external device, and causing said battery (17a...17c) to supply the operation power to said memory device (24) when said memory is not connected to said external device.
Claim 10
Dependent Claim
55 words
A memory including a memory device (24), a battery (17a...17c) for supplying operation power to said memory device (24) and a card (11) on which said memory device (24) and said battery (17a...17c) are disposed, characterised in that the substrate bias voltage of said memory device (24) is the grounding voltage of said battery (17c).
Claim 11
Dependent Claim
55 words
A memory including a memory device (24), a battery (17a...17c) for supplying operation power to said memory device (24) and a card (11) on which said memory device (24) and said battery (17a...17c) are disposed, characterised in that the substrate bias voltage of said memory device (24) is the grounding voltage of said battery (17c).
References Cited (Backward Citations)
No citation records indexed.
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