Patent US5544114A successfully refreshed from Google Patents.
US5544114A
Expired / Lapsed
US
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Integrated circuit memory device with balancing circuit including following amplifier coupled to bit line
Assignee: STMicroelectronics SA
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Filing: 1995-06-07
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Granted: 1996-08-06
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Expires: 2015-06-07
Abstract
Abstract In reading circuits for memories in integrated circuit form, notably non-volatile memories, to obtain a better compromise between reading speed and the reliability of the information read, there is proposed a reading circuit constituted as follows: a differential amplifier, means for the precharging of the bit line before a reading phase and means for the balancing of the input potentials of the differential amplifier before the reading phase. The balancing means comprise a follower amplifier that has one input connected to the output of the differential amplifier and is connected during the balancing phase in such a way that it injects a load current of the bit line in a direction tending to cancel the output voltage to the differential amplifier. A cascode transistor can be used to accelerate the reading.
Inventors
- 👤 Jean-Marie Gaultier
- 👤 Emilio M. Yero
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:18
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/062; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28; G11C7/067; G11C2207/00; G11C2207/06; G11C2207/063
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
186 words
A reading device for reading a memory comprising: a bit line connected to a memory cell of said memory, a reference line, a differential amplifier, having a first input and a second input, a follower amplifier connected in a feedback arrangement between an output of the differential applifier and one of the first input and the second input of the differential amplifier; a first precharging transistor being series connected between the bit line and the first input of the differential amplifier; a second precharging transistor being series connected between the reference line and the second input of the differential amplifier: a current mirror having a copy input connected to the first input of the differential amplifier and a reference input connected to the second input of the differential amplifier; a first intermediate transistor, having a gate connected to a fixed potential, being series connected between the copy input of the current mirror and the first precharging transistor; and a second intermediate transistor, having a gate connected to said fixed potential, being series connected between the reference input of the current mirror and the second precharging transistor.
Claim 2
Dependent Claim
186 words
A reading device for reading a memory comprising: a bit line connected to a memory cell of said memory, a reference line, a differential amplifier, having a first input and a second input, a follower amplifier connected in a feedback arrangement between an output of the differential applifier and one of the first input and the second input of the differential amplifier; a first precharging transistor being series connected between the bit line and the first input of the differential amplifier; a second precharging transistor being series connected between the reference line and the second input of the differential amplifier: a current mirror having a copy input connected to the first input of the differential amplifier and a reference input connected to the second input of the differential amplifier; a first intermediate transistor, having a gate connected to a fixed potential, being series connected between the copy input of the current mirror and the first precharging transistor; and a second intermediate transistor, having a gate connected to said fixed potential, being series connected between the reference input of the current mirror and the second precharging transistor.
Claim 3
Dependent Claim
25 words
The reading device of claim 1 wherein said first intermediate transistor is a P-channel transistor and wherein said fixed potential is a low supply potential.
Claim 4
Dependent Claim
25 words
The reading device of claim 1 wherein said second intermediate transistor is a P-channel transistor and wherein said fixed potential is a low supply potential.
Claim 5
Dependent Claim
20 words
The reading device of claim 1, wherein the first intermediate transistor and the second intermediate transistor are each P-channel transistors.
Claim 6
Dependent Claim
13 words
The reading device of claim 1, wherein the fixed potential is zero volts.
Claim 7
Dependent Claim
29 words
The reading device of claim 1, wherein the first precharging transistor and the second precharging transistor each have a gate connected to a reference potential during a precharging phase.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-06 | 2000-02-05 | 2000-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-06 | 2004-02-05 | 2004-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-06 | 2008-02-05 | 2008-08-06 | $7700.00 | Window Closed / Lapsed |