Single-ended CMOS sense amplifier

Claim 1

A memory device comprising: an array of rows and columns of memory cells, a row line for each row of cells and a column line for each column of cells; each memory cell having an access transistor including a drain, a source-to-drain path, and a gate; the drain of each cell in a column being connected to said column line for the column and the gate of each cell being connected to said row line for the row, a plurality of single-ended sense amplifier circuits, one for each column, each one of said sense amplifier circuits being connected to a separate one of said column lines, each sense amplifier circuit including a detector circuit responsive to a given threshold voltage, the detector circuit having an input coupled to said column line for the respective volumn through a first coupling means, and an output from the detector circuit connected back to said column line through second coupling means, precharge means for precharging the column lines to a selected voltage prior to the beginning of an active cycle, dummy cell means for coupling a selected charge to each said column line at said beginning of an active cycle, said selected charge producing a voltage on said column line above said threshold if a 1 is stored in a selected memory cell, and below said threshold if a 0 is stored, row addressing means for applying an activating voltage to the gates of said access transistors in a selected row by one of said row lines at said beginning of an active cycle, and means for activating said first and second coupling means in sequence with a time delay after said beginning of an active cycle.