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US5204838A Expired / Lapsed US ⏱️ 0.0 years remaining

High speed readout circuit

Assignee: Fujifilm Business Innovation Corp
•
Filing: 1991-08-21
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Granted: 1993-04-20
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Expires: 2011-08-21
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Abstract

Abstract The high speed readout circuit has an amplifier unit and an operating point setting unit and reads data from a memory sense line at high speed. The circuit further includes a unit for setting an operating point of the amplifier unit by short-circuiting the input and output terminals of the amplifier in response to a first control signal and precharging the sense line up to the operating point, and a unit for setting the sense line at a voltage slightly deviating the operating point in response to a second control signal by making use of a Miller capacitance and sensing the variations from the preset voltage during a reading process.

Inventors

  • 👤 Jinshu Son
  • 👤 Nobuaki Miyakawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 03:19
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C7/00; G11C7/06; G11C7/067; H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K5/023; H03K5/22; H03K5/24; H03K5/2472; H03K5/249

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 118 words
A high speed readout circuit for reading out data of a memory unit, comprising: an amplifier unit having an input terminal and an output terminal for sensing variations from a preset voltage on a sense line so as to read out stored data; and an operating point setting unit for setting an operating point of said amplifier by short-circuiting the input and output terminals of said amplifier unit and for precharging said sense line to said operating point in response to a first signal, said operating point setting unit including capacitor means for setting the voltage on said sense line to a value having a predetermined slight deviation from said operating point in response to a second signal.
Claim 2
Dependent Claim 118 words
A high speed readout circuit for reading out data of a memory unit, comprising: an amplifier unit having an input terminal and an output terminal for sensing variations from a preset voltage on a sense line so as to read out stored data; and an operating point setting unit for setting an operating point of said amplifier by short-circuiting the input and output terminals of said amplifier unit and for precharging said sense line to said operating point in response to a first signal, said operating point setting unit including capacitor means for setting the voltage on said sense line to a value having a predetermined slight deviation from said operating point in response to a second signal.
Claim 3
Dependent Claim 17 words
A high speed readout circuit according to claim 1 wherein said amplifier unit includes an inverter circuit.
Claim 4
Dependent Claim 22 words
A high speed readout circuit according to claim 2 wherein said inverter circuit includes two metal oxide semiconductor transistors connected in series.
Claim 5
Dependent Claim 31 words
A high speed readout circuit according to claim 1 wherein said operating point setting unit includes a metal-oxide semiconductor transistor coupled to said input and output terminals of said amplifier unit.
Claim 6
Dependent Claim 28 words
A high speed readout circuit according to claim 4 wherein said capacitor means includes the capacitance of said metal oxide semiconductor transistor of said operating point setting unit.

References Cited (Backward Citations)

JPS5924493A Cited
US4584672A Cited
US4709352A Cited
US4831593A Cited
US4821239A Cited
US4859882A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-04-19 1996-10-19 1997-04-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-04-19 2000-10-19 2001-04-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-04-19 2004-10-19 2005-04-20 $7700.00 Window Closed / Lapsed

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