Process for realizing P-channel MOS transistors having a low threshold voltage in semiconductor integrated circuits for analog applications

Claim 2

A process for forming P-channel MOS transistors having a first threshold voltage in semiconductor integrated circuits for analog applications using CMOS processes, said circuits including resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation, comprising the steps of: providing a first mask over both said resistors and the semiconductor regions where the P-channel transistors are to be formed; doping the polycrystalline layer left exposed by said first mask; providing a second mask for protecting the resistors and the semiconductor regions where said P-channel transistors are to be formed; and N+ implanting the active areas of the N-channel transistors.

Claim 3

A process according to claim 1, wherein a third mask is provided for said resistors during a P+ implantation of the active areas of said P-channel transistors.

Claim 4

A process according to claim 1, wherein said step of doping the polycrystalline layer is for forming gate terminals of said N-channel transistors and of other P-channel transistors having a second threshold voltage higher than the first threshold voltage.

Claim 5

A process according to claim 1, wherein said second mask is removed on completion of the N+ implant step.

Claim 6

A process according to claim 2, wherein active areas of the P-channel transistors are subjected to an additional implant step such that the P-channel transistors have a third threshold voltage lower than the first threshold voltage.

Claim 7

A process according to claim 1, wherein said masks comprise a layer of silicon oxide.

Claim 8

A process for forming P-channel MOS transistors having a first threshold voltage in semiconductor integrated circuits for analog applications using CMOS processes, said circuits including resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-well, comprising the steps of: providing a first mask over both said resistors and the semiconductor regions where the P-channel transistors having a first threshold voltage are to be formed; doping the polycrystalline layer uncovered by said first mask providing a second mask for protecting the resistors and the semiconductor regions where said P-channel transistors are to be formed; and N+ implanting the active areas of the N-channel transistors.

Claim 9

A process for forming P-channel MOS transistors having a first threshold voltage in semiconductor integrated circuits for analog applications using CMOS processes, said circuits including resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-well, comprising the steps of: providing a first mask over both said resistors and the semiconductor regions where the P-channel transistors having a first threshold voltage are to be formed; doping the polycrystalline layer uncovered by said first mask providing a second mask for protecting the resistors and the semiconductor regions where said P-channel transistors are to be formed; and N+ implanting the active areas of the N-channel transistors.

Claim 10

A process according to claim 7, wherein a third mask is provided for said resistors during a P+ implantation of the active areas of said P-channel transistors.

Claim 11

A process according to claim 8 wherein a portion of said resistors is uncovered from said second or said third mask to realize by implantation ohmic contact terminals.

Claim 12

A process according to claim 7 wherein said P-Channel transistors have gate terminals connected to the remaining circuitry by a first metallization layer.

Claim 13

A process for forming P-channel MOS transistors with different threshold voltages in semiconductor integrated circuits having a layer of polycrystalline silicon using CMOS processes, said P-Channel MOS transistors comprising first threshold voltage P-channel MOS transistors, said circuits comprising N-channel MOS transistors, the process comprising the steps of: providing a first mask over said semiconductor regions where said first threshold voltage P-channel MOS transistors are to be formed; doping the polycrystalline layer left exposed by said first mask; providing a second mask for protecting said semiconductor regions where said P-channel MOS transistors are to be formed; N+ implanting active areas of said N-channel MOS transistors; and P+ implanting active areas of said P-channel MOS transistors.

Claim 14

A process for forming P-channel MOS transistors with different threshold voltages in semiconductor integrated circuits having a layer of polycrystalline silicon using CMOS processes, said P-Channel MOS transistors comprising first threshold voltage P-channel MOS transistors, said circuits comprising N-channel MOS transistors, the process comprising the steps of: providing a first mask over said semiconductor regions where said first threshold voltage P-channel MOS transistors are to be formed; doping the polycrystalline layer left exposed by said first mask; providing a second mask for protecting said semiconductor regions where said P-channel MOS transistors are to be formed; N+ implanting active areas of said N-channel MOS transistors; and P+ implanting active areas of said P-channel MOS transistors.

Claim 15

A process according to claim 11, further comprising a step of providing a third mask for said N-channel MOS transistors during said P+ implantation of said active areas of said P-channel MOS transistors.

Claim 16

A process for forming P-channel MOS transistors in semiconductor integrated circuits for analog applications using CMOS processes, the P-channel MOS transistors including first threshold voltage P-channel MOS transistors and second threshold voltage P-channel MOS transistors, the semiconductor integrated circuits having resistors and N-channel MOS transistors, the process comprising the steps of: providing a substrate of P-type semiconductor material; providing a plurality of N-wells in the substrate; providing a layer of polycrystalline silicon; depositing a first layer of silicon oxide to provide a first mask over the resistors and the N-well semiconductor regions where the first threshold voltage P-channel transistors are to be formed; doping the polycrystalline layer left exposed by the first mask to form gate terminals of the N-channel transistors and the second threshold voltage P-channel transistors, the-second threshold voltage being higher than the first threshold voltage; removing the first mask upon completion of said doping step; depositing a second layer of silicon oxide to provide a second mask over the resistors and the N-well semiconductor regions where the first threshold voltage P-channel transistors and the second threshold voltage P-channel transistors are to be formed; N+ implanting active areas of the N-channel transistors; removing the second mask upon completion of said N+ implanting step; depositing a third layer of silicon oxide to provide a third mask over the resistors and the N-channel transistors; and P+ implanting active areas of the first threshold voltage P-channel transistors and the second threshold voltage P-channel transistors.

Claim 17

A process for forming P-channel MOS transistors in semiconductor integrated circuits for analog applications using CMOS processes, the P-channel MOS transistors including first threshold voltage P-channel MOS transistors and second threshold voltage P-channel MOS transistors, the semiconductor integrated circuits having resistors and N-channel MOS transistors, the process comprising the steps of: providing a substrate of P-type semiconductor material; providing a plurality of N-wells in the substrate; providing a layer of polycrystalline silicon; depositing a first layer of silicon oxide to provide a first mask over the resistors and the N-well semiconductor regions where the first threshold voltage P-channel transistors are to be formed; doping the polycrystalline layer left exposed by the first mask to form gate terminals of the N-channel transistors and the second threshold voltage P-channel transistors, the-second threshold voltage being higher than the first threshold voltage; removing the first mask upon completion of said doping step; depositing a second layer of silicon oxide to provide a second mask over the resistors and the N-well semiconductor regions where the first threshold voltage P-channel transistors and the second threshold voltage P-channel transistors are to be formed; N+ implanting active areas of the N-channel transistors; removing the second mask upon completion of said N+ implanting step; depositing a third layer of silicon oxide to provide a third mask over the resistors and the N-channel transistors; and P+ implanting active areas of the first threshold voltage P-channel transistors and the second threshold voltage P-channel transistors.

Claim 18

The process of claim 13 wherein said first masking step, said doping step, and said P+ implanting step alter a work function difference between gate terminals of the first threshold voltage transistors and N-wells where the first threshold voltage transistors are formed without altering distribution of dopant in the N-wells.