EP0178991A2
Expired / Lapsed
EP
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A complementary semiconductor device having high switching speed and latchup-free capability
Assignee: Fujitsu Ltd
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Filing: 1985-10-10
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Granted: —
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Expires: 2005-10-10
Abstract
Abstract A complementary type semiconductor device comprises n-channel FETs (n-Tr) and different types (p-Tr,, p-Tr z ) of p-channel FETs formed in an n - -type semiconductor substrate (1). p-channel FETs of a first type (p-Tr,) and n-channel FETs (n-Tr), both having deep well regions (9a, 2) are employed for input/output circuits arranged in a peripheral area of the substrate (1) so that these transistors are directly connected to exterior circuit through bonding wires and the like. The transistors (p-Tr,) are seldom disturbed by undesirable noises from the external circuits, because these FETs are suitable for preventing the latchup effect of the circuits. While the other p-channel FETs (p-Tr 2 ) having n-type sub-well regions (9b) beneath their gate insulator layers (5) selectively, and thus resulting in relatively small junction capacitances, are employed in circuits needed for high switching speed and arranged in the inner area of the substrate. By the selective adoption of the p-channel FETs of different types corresponding to the requirements of the associated circuits, a complementary semiconductor device having highly reliable operation and high switching speed is achieved.
Inventors
- 👤 Takehide Shirato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 06:07
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
255 words
A complementary semiconductor device formed in a semiconductor substrate (1) having a first conductivity type characterized in that it comprises : a well region (2) of second conductivity type formed in said semiconductor substrate (1), having higher dopant concentration than that of said semiconductor substrate ( 1), said first conductivity type being opposite to said second conductivity type; a well region (9a ; 109a) of said first conductivity type formed in said substrate (1), having higher dopant concentration than that of said substrate (1); a sub-well region(9b) of said first conductivity type formed in said substrate (1) having higher dopant concentration than that of said semiconductor substrate (1); a first conductivity type channel MIS field effect transistor (n-Tr) formed in said well region (2) of second conductivity type; a second conductivity type channel MIS field effect transistor (p-Tri p-Tr l ') of first type or second type formed in said well region (9a; 109a) of said first conductivity type, having a source region (7a) and a drain region (8a), whereby at least a part of said source region (7a) and a part of said drain region (8a) are in contact with said well region (9a; 109a) of first conductivity type; and a second conductivity type channel MIS field effect transistor of thirdtype (p-Tr 2 ) having a source region (7b) and a drain region (8b) formed in said substrate and a gate insulator (5) formed on said substrate, said sub-well region (9b) being selectively formed in said semiconductor substrate (1) beneath said gate insulator (5).
Claim 2
Dependent Claim
255 words
A complementary semiconductor device formed in a semiconductor substrate (1) having a first conductivity type characterized in that it comprises : a well region (2) of second conductivity type formed in said semiconductor substrate (1), having higher dopant concentration than that of said semiconductor substrate ( 1), said first conductivity type being opposite to said second conductivity type; a well region (9a ; 109a) of said first conductivity type formed in said substrate (1), having higher dopant concentration than that of said substrate (1); a sub-well region(9b) of said first conductivity type formed in said substrate (1) having higher dopant concentration than that of said semiconductor substrate (1); a first conductivity type channel MIS field effect transistor (n-Tr) formed in said well region (2) of second conductivity type; a second conductivity type channel MIS field effect transistor (p-Tri p-Tr l ') of first type or second type formed in said well region (9a; 109a) of said first conductivity type, having a source region (7a) and a drain region (8a), whereby at least a part of said source region (7a) and a part of said drain region (8a) are in contact with said well region (9a; 109a) of first conductivity type; and a second conductivity type channel MIS field effect transistor of thirdtype (p-Tr 2 ) having a source region (7b) and a drain region (8b) formed in said substrate and a gate insulator (5) formed on said substrate, said sub-well region (9b) being selectively formed in said semiconductor substrate (1) beneath said gate insulator (5).
Claim 3
Dependent Claim
84 words
A complementary semiconductor device according to claim 1, characterized in that said second conductivity type channel MIS field effect transistors of first type and/or second type (p-Tr l ; p-Tr 1 ') are disposed in at least one input/output circuit of said complementary semiconductor device wherein said second conductivity type channel MIS field effect transistors of first type and/or second type (p-Tr l ; p-Tr 1 ') are directly connected to an exterior circuit out of said complementary semiconductor device through a connecting means.
Claim 4
Dependent Claim
49 words
A complementary semiconductor device according to claim 1, characterized in that said second type channel MIS field effect transistor of third type(p-Tr 2 ) is employed in an inner circuit of said complementary semiconductor device, said inner circuit being defined as a circuit except at least an output/input circuit.
Claim 5
Dependent Claim
29 words
A complementary semiconductor device according to claim 2, characterized in that said at least one output/input circuit is formed in a peripheral area (Cl) of said semiconductor substrate (1).
Claim 6
Dependent Claim
28 words
A complementary semiconductor device according to claim 3, characterized in that at least said inner circuit is formed in a central portion (C2) of said semiconductor substrate (1).
Claim 7
Dependent Claim
23 words
A complementary semiconductor device according to claim 2, characterized in that said connecting means comprises a bonding wire (W) and/or a lead terminal.
Claim 8
Dependent Claim
32 words
A complementary semiconductor device according to claim 1 or 3, characterized in that said second conductivity type channel MIS field effect transistor of third type (p-Tr 2 ) has low junction capacitances.
Claim 9
Dependent Claim
59 words
A complementary semiconductor device according to claim 1, characterized in that said second conductivity type channel MIS field effect transistor of second type (p-Tr 1 ') comprises two rectangular windows (16) in said well region (109a) of said first conductivity type,whereby said source region (7a) and said drain region (8a) contact directly said substrate (1) through said windows (16).
Claim 10
Dependent Claim
65 words
A complementary semiconductor device of claim 1, characterized in that said sub-well region (9b) of said second conductivity type MIS field effect transistor of third type (p-Tr 2 ) is formed in the portion of said semiconductor substrate (1) between said source region (7b) and said drain region (8b), being in contact with a part of said source region (7b) and said drain region (8b).
Claim 11
Dependent Claim
37 words
lO. A complementary semiconductor device according to any of claims 1 to 9, characterized in that said MIS field effect transistors (n-Tr, p-Tr 1 , p-Tr 1 ', p- Tr 2 ) include MOS field effect transistors.
References Cited (Backward Citations)
No citation records indexed.
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