US5528176A
Expired / Lapsed
US
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Register with duplicate decoders for configurable cellular array
Assignee: Xilinx Inc
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Filing: 1995-06-07
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Granted: 1996-06-18
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Expires: 2015-06-07
Abstract
Abstract An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.
Inventors
- 👤 Thomas A. Kean
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:24
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17758; H03K19/1733; H03K19/1737; G; G06; G06F; G06F30/00; G06F30/30; G06F30/34; H03K19/17704; H03K19/17752; H03K19/17756
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
85 words
A decoding system in an array of cells comprising: a plurality of bit lines placed in operative relation to said array; a plurality of word lines placed in operative relation to said array; a plurality of address decoders, wherein each address decoder is coupled to a word line; and a plurality of duplicate decoders, wherein each duplicate decoder is associated with a predetermined word or bit line, said duplicate decoder and the corresponding address decoder coupled to said predetermined word line via a logic gate.
Claim 2
Dependent Claim
85 words
A decoding system in an array of cells comprising: a plurality of bit lines placed in operative relation to said array; a plurality of word lines placed in operative relation to said array; a plurality of address decoders, wherein each address decoder is coupled to a word line; and a plurality of duplicate decoders, wherein each duplicate decoder is associated with a predetermined word or bit line, said duplicate decoder and the corresponding address decoder coupled to said predetermined word line via a logic gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-18 | 1999-12-18 | 2000-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-18 | 2003-12-18 | 2004-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-18 | 2007-12-18 | 2008-06-18 | $7700.00 | Window Closed / Lapsed |